Searched refs:IsPre (Results 1 – 9 of 9) sorted by relevance
43 bool IsPre; member
1047 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1057 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1060 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1062 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1064 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1073 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in tryIndexedLoad()1075 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in tryIndexedLoad()1077 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1086 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in tryIndexedLoad()1088 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in tryIndexedLoad()[all …]
1192 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1202 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1205 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1207 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1209 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1218 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in tryIndexedLoad()1220 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in tryIndexedLoad()1222 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1231 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in tryIndexedLoad()1233 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in tryIndexedLoad()[all …]
1272 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC; in tryIndexedLoad() local1282 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()1285 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1287 Opcode = IsPre ? AArch64::LDRSWpre : AArch64::LDRSWpost; in tryIndexedLoad()1289 Opcode = IsPre ? AArch64::LDRWpre : AArch64::LDRWpost; in tryIndexedLoad()1298 Opcode = IsPre ? AArch64::LDRSHXpre : AArch64::LDRSHXpost; in tryIndexedLoad()1300 Opcode = IsPre ? AArch64::LDRSHWpre : AArch64::LDRSHWpost; in tryIndexedLoad()1302 Opcode = IsPre ? AArch64::LDRHHpre : AArch64::LDRHHpost; in tryIndexedLoad()1311 Opcode = IsPre ? AArch64::LDRSBXpre : AArch64::LDRSBXpost; in tryIndexedLoad()1313 Opcode = IsPre ? AArch64::LDRSBWpre : AArch64::LDRSBWpost; in tryIndexedLoad()[all …]
727 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()729 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()772 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
49 bool IsPre; member
832 MatchInfo.IsPre = findPreIndexCandidate(MI, MatchInfo.Addr, MatchInfo.Base, in matchCombineIndexedLoadStore()834 if (!MatchInfo.IsPre && in matchCombineIndexedLoadStore()877 MIB.addImm(MatchInfo.IsPre); in applyCombineIndexedLoadStore()
3000 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument
3180 bool IsPre, MachineRegisterInfo &MRI) const { in isIndexingLegal() argument