Searched refs:IsSP (Results 1 – 12 of 12) sorted by relevance
170 VIXL_ASSERT(!reg.IsSP()); in Operand()181 VIXL_ASSERT(!reg.IsSP()); in Operand()268 VIXL_ASSERT(!regoffset.IsSP()); in MemOperand()288 VIXL_ASSERT(regoffset.Is64Bits() && !regoffset.IsSP()); in MemOperand()315 VIXL_ASSERT(regoffset_.Is64Bits() && !regoffset_.IsSP()); in MemOperand()329 VIXL_ASSERT(!regoffset_.IsSP()); in MemOperand()
473 temp = rd.IsSP() ? temps.AcquireSameSizeAs(rd) : rd; in MoveImmediateHelper()504 if (rd.IsSP()) { in MoveImmediateHelper()520 if (IsImmMovz(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()527 } else if (IsImmMovn(imm, reg_size) && !dst.IsSP()) { in OneInstrMoveImmediateHelper()905 PreShiftImmMode mode = rn.IsSP() ? kNoShift : kAnyShift; in LogicalMacro()1241 VIXL_ASSERT(!rd.IsZero() && !rd.IsSP()); in CselHelper()1242 VIXL_ASSERT(left.IsImmediate() || !left.GetRegister().IsSP()); in CselHelper()1243 VIXL_ASSERT(right.IsImmediate() || !right.GetRegister().IsSP()); in CselHelper()1788 if (rd.IsSP()) { in AddSubMacro()1792 } else if (rn.IsSP()) { in AddSubMacro()
189 if (xn.IsZero() && xd.IsSP()) { in Addpl()239 } else if (xd.IsSP() || xn.IsSP()) { in Addpl()260 if (xn.IsZero() && xd.IsSP()) { in Addvl()296 } else if (xd.IsSP() || xn.IsSP()) { in Addvl()
299 bool IsSP() const { return IsRegister() && (code_ == kSPRegInternalCode); } in IsSP() function
2575 if (rd.IsSP() || rm.IsSP()) { in mov()5360 if (rn.IsSP() || rd.IsSP()) { in AddSub()5361 VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags))); in AddSub()
490 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm; in rewriteT2FrameIndex() local491 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()513 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()515 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()531 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()532 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
537 const bool IsSP = Opcode == ARM::t2ADDspImm12 || Opcode == ARM::t2ADDspImm; in rewriteT2FrameIndex() local538 if (IsSP || Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) { in rewriteT2FrameIndex()560 MI.setDesc(IsSP ? TII.get(ARM::t2SUBspImm) : TII.get(ARM::t2SUBri)); in rewriteT2FrameIndex()562 MI.setDesc(IsSP ? TII.get(ARM::t2ADDspImm) : TII.get(ARM::t2ADDri)); in rewriteT2FrameIndex()578 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()579 : IsSP ? ARM::t2ADDspImm12 : ARM::t2ADDri12; in rewriteT2FrameIndex()
286 static bool IsSP(const MachineOperand &MO) { in INITIALIZE_PASS()448 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()517 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUR1SP()535 if (!IsSP(MI->getOperand(0)) || !IsSP(MI->getOperand(1))) in ReduceADDIUToADDIUSP()
18234 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18265 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18279 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() && in vld1()18295 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18325 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld1()18338 (nreglist.GetLength() == 1) && !rm.IsPC() && !rm.IsSP() && in vld1()18614 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18639 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18655 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()18672 !rm.IsPC() && !rm.IsSP() && (!rn.IsPC() || AllowUnpredictable())) { in vld2()[all …]
146 bool IsSP() const { return GetCode() == kSpCode; } in IsSP() function
1076 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) || in Add()1082 !operand.GetBaseRegister().IsSP() && in Add()1085 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && in Add()2086 operand.GetBaseRegister().IsSP() && in Ldr()4418 operand.GetBaseRegister().IsSP() && in Str()