| /external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in emitInstruction() local
160 &IsStore); in emitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in emitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 150 bool IsStore; in EmitInstruction() local
152 &IsStore); in EmitInstruction()
158 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
203 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
204 if (IsStore) in isBasePlusOffsetMemoryAccess()
205 *IsStore = false; in isBasePlusOffsetMemoryAccess()
235 if (IsStore) in isBasePlusOffsetMemoryAccess()
236 *IsStore = true; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 158 bool IsStore = false; in EmitInstruction() local
160 &IsStore); in EmitInstruction()
166 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
211 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
212 if (IsStore) in isBasePlusOffsetMemoryAccess()
213 *IsStore = false; in isBasePlusOffsetMemoryAccess()
243 if (IsStore) in isBasePlusOffsetMemoryAccess()
244 *IsStore = true; in isBasePlusOffsetMemoryAccess()
251 if (IsStore) in isBasePlusOffsetMemoryAccess()
252 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
|
| /external/llvm-project/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 395 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
402 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
423 bool IsStore = Ldst->mayStore(); in canSinkLoadStoreTo() local
433 if (IsStore && MI->mayLoad()) in canSinkLoadStoreTo()
444 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
454 if (IsStore) { in changeToAddrMode()
461 if (IsStore) in changeToAddrMode()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARC/ |
| D | ARCOptAddrMode.cpp | 395 bool IsStore = Ldst->mayStore(); in canHoistLoadStoreTo() local
402 if (IsStore && MI->mayLoad()) in canHoistLoadStoreTo()
423 bool IsStore = Ldst->mayStore(); in canSinkLoadStoreTo() local
433 if (IsStore && MI->mayLoad()) in canSinkLoadStoreTo()
444 bool IsStore = Ldst.mayStore(); in changeToAddrMode() local
454 if (IsStore) { in changeToAddrMode()
461 if (IsStore) in changeToAddrMode()
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | EfficiencySanitizer.cpp | 196 bool instrumentFastpath(Instruction *I, const DataLayout &DL, bool IsStore,
650 bool IsStore; in instrumentLoadOrStore() local
654 IsStore = false; in instrumentLoadOrStore()
658 IsStore = true; in instrumentLoadOrStore()
662 IsStore = true; in instrumentLoadOrStore()
666 IsStore = true; in instrumentLoadOrStore()
680 if (IsStore) in instrumentLoadOrStore()
686 OnAccessFunc = IsStore ? EsanUnalignedStoreN : EsanUnalignedLoadN; in instrumentLoadOrStore()
692 instrumentFastpath(I, DL, IsStore, Addr, Alignment)) { in instrumentLoadOrStore()
697 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx]; in instrumentLoadOrStore()
[all …]
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
366 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
372 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
680 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
697 !SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
702 if (SwapVector[UseOfUseIdx].IsStore) { in recordUnoptimizableWebs()
719 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
727 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
793 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
1005 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 37 bit IsStore = 0;
53 let TSFlags{6-6} = IsStore;
|
| /external/llvm-project/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 36 bit IsStore = false;
52 let TSFlags{6...6} = IsStore;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| D | NVPTXInstrFormats.td | 36 bit IsStore = 0;
52 let TSFlags{6-6} = IsStore;
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 79 unsigned int IsStore : 1; member
366 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
372 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
675 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
691 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
699 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
764 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
969 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 75 unsigned int IsStore : 1; member
366 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
372 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
680 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
696 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
704 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
770 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
982 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 773 bit IsStore = ?;
1067 let IsStore = 1;
1072 let IsStore = 1;
1079 let IsStore = 1;
1084 let IsStore = 1;
1089 let IsStore = 1;
1094 let IsStore = 1;
1099 let IsStore = 1;
1104 let IsStore = 1;
1110 let IsStore = 1;
[all …]
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 771 bit IsStore = ?;
1069 let IsStore = true;
1074 let IsStore = true;
1081 let IsStore = true;
1086 let IsStore = true;
1091 let IsStore = true;
1096 let IsStore = true;
1101 let IsStore = true;
1106 let IsStore = true;
1111 let IsStore = true;
[all …]
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUInstructions.td | 343 let IsStore = 1;
421 let IsStore = 1;
428 let IsStore = 1;
438 let IsStore = 1;
444 let IsStore = 1;
503 let IsStore = 1;
509 let IsStore = 1;
|
| D | SIRegisterInfo.cpp | 691 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
695 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
696 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
697 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32 in spillVGPRtoAGPR()
716 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
719 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
765 bool IsStore = Desc->mayStore(); in buildSpillLoadStore() local
851 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
860 const bool NeedSuperRegDef = NumSubRegs > 1 && IsStore && i == 0; in buildSpillLoadStore()
875 if (IsStore) { in buildSpillLoadStore()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIRegisterInfo.cpp | 559 bool IsStore = MI->mayStore(); in spillVGPRtoAGPR() local
563 unsigned Dst = IsStore ? Reg : ValueReg; in spillVGPRtoAGPR()
564 unsigned Src = IsStore ? ValueReg : Reg; in spillVGPRtoAGPR()
565 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32 in spillVGPRtoAGPR()
582 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
585 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
631 bool IsStore = Desc.mayStore(); in buildSpillLoadStore() local
692 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
704 if (IsStore) in buildSpillLoadStore()
716 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
[all …]
|
| D | AMDGPUInstructions.td | 341 let IsStore = 1;
414 let IsStore = 1;
421 let IsStore = 1;
431 let IsStore = 1;
437 let IsStore = 1;
495 let IsStore = 1;
501 let IsStore = 1;
|
| /external/llvm/lib/CodeGen/ |
| D | AtomicExpandPass.cpp | 51 bool IsStore, bool IsLoad);
227 bool IsStore, IsLoad; in runOnFunction() local
231 IsStore = false; in runOnFunction()
236 IsStore = true; in runOnFunction()
242 IsStore = IsLoad = true; in runOnFunction()
253 IsStore = IsLoad = true; in runOnFunction()
257 MadeChange |= bracketInstWithFences(I, FenceOrdering, IsStore, IsLoad); in runOnFunction()
324 bool IsStore, bool IsLoad) { in bracketInstWithFences() argument
327 auto LeadingFence = TLI->emitLeadingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
329 auto TrailingFence = TLI->emitTrailingFence(Builder, Order, IsStore, IsLoad); in bracketInstWithFences()
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| /external/llvm-project/llvm/utils/TableGen/ |
| D | X86FoldTablesEmitter.cpp | 104 bool IsStore = false; member in __anon446c46d20111::X86FoldTablesEmitter::X86FoldTableEntry
121 if (IsStore) in print()
479 Result.IsStore = true; in addEntryWithFlags()
|
| /external/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 436 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
437 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
438 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
455 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2SizeReduction.cpp | 466 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
485 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
|