Searched refs:IsUintN (Results 1 – 13 of 13) sorted by relevance
| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 740 bool IsUintN(unsigned n) const { in IsUintN() function
741 return !is_negative_ && vixl::IsUintN(n, raw_bits_); in IsUintN()
744 bool IsUint8() const { return IsUintN(8); } in IsUint8()
745 bool IsUint16() const { return IsUintN(16); } in IsUint16()
746 bool IsUint32() const { return IsUintN(32); } in IsUint32()
747 bool IsUint64() const { return IsUintN(64); } in IsUint64()
755 return is_negative_ ? IsIntN(n) : IsUintN(n); in FitsInBits()
764 return IsUintN(zd.GetLaneSizeInBits()); in FitsInUnsignedLane()
821 if (unshifted.IsUintN(zd.GetLaneSizeInBits() - kShift)) { in TryEncodeAsShiftedIntNForLane()
868 if (vixl::IsUintN(N, raw_bits_ >> kShift)) { in TryEncodeAsShiftedUintNForLane()
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| D | cpu-aarch64.h | 229 VIXL_ASSERT(IsUintN(kAddressTagWidth, tag)); in SetPointerTag()
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| D | macro-assembler-aarch64.h | 3804 if (imm.IsUintN(7)) { in Cmphi()
3823 if (imm.IsUintN(7)) { in Cmphs()
3863 if (imm.IsUintN(7)) { in Cmplo()
3882 if (imm.IsUintN(7)) { in Cmpls()
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| D | macro-assembler-aarch64.cc | 1884 IsUintN(rd.GetSizeInBits() == kXRegSize ? kXRegSizeLog2 : kWRegSizeLog2, in AddSubWithCarryMacro()
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| D | disasm-aarch64.cc | 5827 VIXL_ASSERT(IsUintN(8 << lane_bytes_log2, value)); in SVEMoveMaskPreferred()
10773 VIXL_ASSERT(IsUintN(width, bits)); in SubstituteIntField()
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| D | assembler-aarch64.h | 5949 VIXL_ASSERT(IsUintN(hibit - lobit + 1, imm)); in ImmUnsignedField()
6016 VIXL_ASSERT(IsUintN(WhichPowerOf2(lane_size), immr)); in SVEImmRotate()
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| D | logic-aarch64.cc | 596 VIXL_ASSERT(IsUintN(lane_size, value)); in add_uint()
1195 VIXL_ASSERT(IsUintN(lane_size, value)); in sub_uint()
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| D | simulator-aarch64.cc | 47 VIXL_ASSERT(IsUintN(width, bits) || IsIntN(width, bits)); in SetBits()
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| /external/vixl/src/ |
| D | utils-vixl.h | 111 inline bool IsUintN(unsigned n, uint32_t x) { in IsUintN() function
116 inline bool IsUintN(unsigned n, int32_t x) { in IsUintN() function
121 inline bool IsUintN(unsigned n, uint64_t x) { in IsUintN() function
126 inline bool IsUintN(unsigned n, int64_t x) { in IsUintN() function
132 return IsUintN(n, x); in is_uintn()
168 inline bool IsUint##N(int64_t x) { return IsUintN(N, x); } \
170 return IsUintN(N, x); \
1385 VIXL_ASSERT(IsUintN(size_in_bits, value)); in RawbitsWithSizeToFP()
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| /external/vixl/test/ |
| D | test-api.cc | 165 VIXL_CHECK(IsUintN(test_vector[i].n, test_vector[i].x)); \ in TEST()
167 VIXL_CHECK(!IsUintN(test_vector[i].n, test_vector[i].x)); \ in TEST()
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| /external/vixl/test/aarch64/ |
| D | test-api-aarch64.cc | 740 VIXL_CHECK(!IntegerOperand(-1).IsUintN(8)); in TEST()
741 VIXL_CHECK(IntegerOperand(0).IsUintN(8)); in TEST()
742 VIXL_CHECK(IntegerOperand(1).IsUintN(8)); in TEST()
743 VIXL_CHECK(IntegerOperand(0xff).IsUintN(8)); in TEST()
744 VIXL_CHECK(!IntegerOperand(0x100).IsUintN(8)); in TEST()
751 VIXL_CHECK(!IntegerOperand(-1).IsUintN(64)); in TEST()
752 VIXL_CHECK(IntegerOperand(0).IsUintN(64)); in TEST()
753 VIXL_CHECK(IntegerOperand(UINT64_MAX).IsUintN(64)); in TEST()
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| D | test-utils-aarch64.cc | 365 VIXL_ASSERT(IsUintN(lane_size, expected) || in EqualSVELane()
392 VIXL_ASSERT(IsUintN(p_bits_per_lane, expected)); in EqualSVELane()
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 226 if (IsUintN(16, imm)) { in HandleOutOfBoundsImmediate()
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