| /external/llvm-project/llvm/include/llvm/Transforms/Instrumentation/ |
| D | AddressSanitizerCommon.h | 25 bool IsWrite; variable
32 InterestingMemoryOperand(Instruction *I, unsigned OperandNo, bool IsWrite,
35 : IsWrite(IsWrite), OpType(OpType), Alignment(Alignment), in IsWrite() argument
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| /external/llvm-project/llvm/lib/Transforms/Instrumentation/ |
| D | MemProfiler.cpp | 150 bool IsWrite; member
174 Value *Addr, uint32_t TypeSize, bool IsWrite);
178 bool IsWrite);
336 Access.IsWrite = false; in isInterestingMemoryAccess()
343 Access.IsWrite = true; in isInterestingMemoryAccess()
351 Access.IsWrite = true; in isInterestingMemoryAccess()
359 Access.IsWrite = true; in isInterestingMemoryAccess()
374 Access.IsWrite = true; in isInterestingMemoryAccess()
378 Access.IsWrite = false; in isInterestingMemoryAccess()
416 uint32_t TypeSize, bool IsWrite) { in instrumentMaskedLoadOrStore() argument
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| D | ThreadSanitizer.cpp | 450 const bool IsWrite = isa<StoreInst>(*I); in chooseInstructionsToInstrument() local
451 Value *Addr = IsWrite ? cast<StoreInst>(I)->getPointerOperand() in chooseInstructionsToInstrument()
457 if (!IsWrite) { in chooseInstructionsToInstrument()
492 if (IsWrite) { in chooseInstructionsToInstrument()
614 const bool IsWrite = isa<StoreInst>(*II.Inst); in instrumentLoadOrStore() local
615 Value *Addr = IsWrite ? cast<StoreInst>(II.Inst)->getPointerOperand() in instrumentLoadOrStore()
627 if (IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
645 if (!IsWrite && isVtableAccess(II.Inst)) { in instrumentLoadOrStore()
652 const unsigned Alignment = IsWrite ? cast<StoreInst>(II.Inst)->getAlignment() in instrumentLoadOrStore()
657 (IsWrite ? cast<StoreInst>(II.Inst)->isVolatile() in instrumentLoadOrStore()
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| D | AddressSanitizer.cpp | 631 Value *Addr, uint32_t TypeSize, bool IsWrite,
635 uint32_t TypeSize, bool IsWrite,
641 bool IsWrite, size_t AccessSizeIndex,
1404 bool IsWrite = F->getName().startswith("llvm.masked.store."); in getInterestingMemoryOperands() local
1406 unsigned OpOffset = IsWrite ? 1 : 0; in getInterestingMemoryOperands()
1407 if (IsWrite ? !ClInstrumentWrites : !ClInstrumentReads) in getInterestingMemoryOperands()
1419 Interesting.emplace_back(I, OpOffset, IsWrite, Ty, Alignment, Mask); in getInterestingMemoryOperands()
1489 uint32_t TypeSize, bool IsWrite, in doInstrumentAddress() argument
1497 return Pass->instrumentAddress(I, InsertBefore, Addr, TypeSize, IsWrite, in doInstrumentAddress()
1500 IsWrite, nullptr, UseCalls, Exp); in doInstrumentAddress()
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| D | HWAddressSanitizer.cpp | 216 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
721 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
729 (IsWrite << HWASanAccessInfo::IsWriteShift) + in instrumentMemAccessInline()
851 IRB.CreateCall(HwasanMemoryAccessCallback[O.IsWrite][AccessSizeIndex], in instrumentMemAccess()
854 instrumentMemAccessInline(Addr, O.IsWrite, AccessSizeIndex, O.getInsn()); in instrumentMemAccess()
857 IRB.CreateCall(HwasanMemoryAccessCallbackSized[O.IsWrite], in instrumentMemAccess()
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmInstrumentation.cpp | 211 bool IsWrite,
215 bool IsWrite,
222 void InstrumentMemOperand(X86Operand &Op, unsigned AccessSize, bool IsWrite,
280 X86Operand &Op, unsigned AccessSize, bool IsWrite, in InstrumentMemOperand() argument
287 InstrumentMemOperandSmall(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
289 InstrumentMemOperandLarge(Op, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMemOperand()
412 const bool IsWrite = MII.get(Inst.getOpcode()).mayStore(); in InstrumentMOV() local
425 InstrumentMemOperand(MemOp, AccessSize, IsWrite, RegCtx, Ctx, Out); in InstrumentMOV()
582 bool IsWrite,
587 bool IsWrite,
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| /external/llvm/lib/Transforms/Instrumentation/ |
| D | AddressSanitizer.cpp | 480 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
486 Value *Addr, uint32_t TypeSize, bool IsWrite,
489 uint32_t TypeSize, bool IsWrite,
495 bool IsWrite, size_t AccessSizeIndex,
938 bool *IsWrite, in isInterestingMemoryAccess() argument
948 *IsWrite = false; in isInterestingMemoryAccess()
954 *IsWrite = true; in isInterestingMemoryAccess()
960 *IsWrite = true; in isInterestingMemoryAccess()
966 *IsWrite = true; in isInterestingMemoryAccess()
1031 bool IsWrite = false; in instrumentMop() local
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| D | ThreadSanitizer.cpp | 461 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
462 Value *Addr = IsWrite in instrumentLoadOrStore()
468 if (IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
486 if (!IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
492 const unsigned Alignment = IsWrite in instrumentLoadOrStore()
499 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
501 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; in instrumentLoadOrStore()
503 if (IsWrite) NumInstrumentedWrites++; in instrumentLoadOrStore()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Instrumentation/ |
| D | AddressSanitizer.cpp | 620 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
628 Value *Addr, uint32_t TypeSize, bool IsWrite,
632 uint32_t TypeSize, bool IsWrite,
638 bool IsWrite, size_t AccessSizeIndex,
1345 bool *IsWrite, in isInterestingMemoryAccess() argument
1360 *IsWrite = false; in isInterestingMemoryAccess()
1366 *IsWrite = true; in isInterestingMemoryAccess()
1372 *IsWrite = true; in isInterestingMemoryAccess()
1378 *IsWrite = true; in isInterestingMemoryAccess()
1392 *IsWrite = true; in isInterestingMemoryAccess()
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| D | HWAddressSanitizer.cpp | 210 void instrumentMemAccessInline(Value *Ptr, bool IsWrite,
215 Value *isInterestingMemoryAccess(Instruction *I, bool *IsWrite,
504 bool *IsWrite, in isInterestingMemoryAccess() argument
519 *IsWrite = false; in isInterestingMemoryAccess()
525 *IsWrite = true; in isInterestingMemoryAccess()
531 *IsWrite = true; in isInterestingMemoryAccess()
537 *IsWrite = true; in isInterestingMemoryAccess()
607 void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, in instrumentMemAccessInline() argument
610 const int64_t AccessInfo = Recover * 0x20 + IsWrite * 0x10 + AccessSizeIndex; in instrumentMemAccessInline()
718 bool IsWrite = false; in instrumentMemAccess() local
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| D | ThreadSanitizer.cpp | 522 bool IsWrite = isa<StoreInst>(*I); in instrumentLoadOrStore() local
523 Value *Addr = IsWrite in instrumentLoadOrStore()
536 if (IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
554 if (!IsWrite && isVtableAccess(I)) { in instrumentLoadOrStore()
560 const unsigned Alignment = IsWrite in instrumentLoadOrStore()
567 OnAccessFunc = IsWrite ? TsanWrite[Idx] : TsanRead[Idx]; in instrumentLoadOrStore()
569 OnAccessFunc = IsWrite ? TsanUnalignedWrite[Idx] : TsanUnalignedRead[Idx]; in instrumentLoadOrStore()
571 if (IsWrite) NumInstrumentedWrites++; in instrumentLoadOrStore()
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| /external/compiler-rt/lib/esan/ |
| D | esan.cpp | 65 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite) { in processRangeAccess() argument
67 IsWrite ? 'w' : 'r', Addr, Size); in processRangeAccess()
72 processRangeAccessWorkingSet(PC, Addr, Size, IsWrite); in processRangeAccess()
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| D | working_set.h | 28 bool IsWrite);
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| D | esan.h | 45 void processRangeAccess(uptr PC, uptr Addr, int Size, bool IsWrite);
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| D | working_set.cpp | 82 bool IsWrite) { in processRangeAccessWorkingSet() argument
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| /external/llvm-project/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 691 bool IsWrite = Access.getInt(); in createCheckForAccess() local
692 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in createCheckForAccess()
732 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
734 if (IsWrite) in canCheckPtrAtRT()
738 AccessInfos.emplace_back(Ptr, IsWrite); in canCheckPtrAtRT()
893 bool IsWrite = AC.getInt(); in processMemAccesses() local
897 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
902 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
906 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
923 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl.h | 200 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
250 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
279 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
287 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
295 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| /external/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 609 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
610 MemAccessInfo Access(Ptr, IsWrite); in canCheckPtrAtRT()
612 if (IsWrite) in canCheckPtrAtRT()
634 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in canCheckPtrAtRT()
749 bool IsWrite = AC.getInt(); in processMemAccesses() local
753 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
758 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
762 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
779 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
784 if (IsWrite) in processMemAccesses()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | LoopAccessAnalysis.cpp | 688 bool IsWrite = Access.getInt(); in createCheckForAccess() local
689 RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE); in createCheckForAccess()
725 bool IsWrite = Accesses.count(MemAccessInfo(Ptr, true)); in canCheckPtrAtRT() local
726 MemAccessInfo Access(Ptr, IsWrite); in canCheckPtrAtRT()
728 if (IsWrite) in canCheckPtrAtRT()
867 bool IsWrite = AC.getInt(); in processMemAccesses() local
871 bool IsReadOnlyPtr = ReadOnlyPtr.count(Ptr) && !IsWrite; in processMemAccesses()
876 assert(((IsReadOnlyPtr && UseDeferred) || IsWrite || in processMemAccesses()
880 MemAccessInfo Access(Ptr, IsWrite); in processMemAccesses()
897 if ((IsWrite || IsReadOnlyPtr) && SetHasWrite) { in processMemAccesses()
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| /external/llvm-project/compiler-rt/lib/tsan/rtl/ |
| D | tsan_rtl.h | 207 DCHECK_EQ(kAccessIsWrite, IsWrite()); in SetWrite()
257 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite() function
286 DCHECK_EQ(v, (!IsWrite() && !kIsWrite) || (IsAtomic() && kIsAtomic)); in IsBothReadsOrAtomic()
294 (IsAtomic() == kIsAtomic && !IsWrite() <= !kIsWrite)); in IsRWNotWeaker()
302 (IsAtomic() == kIsAtomic && !IsWrite() >= !kIsWrite)); in IsRWWeakerOrEqual()
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| D | tsan_rtl_report.cpp | 174 mop->write = s.IsWrite(); in AddMemoryAccess()
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| /external/compiler-rt/lib/tsan/tests/unit/ |
| D | tsan_shadow_test.cc | 28 EXPECT_EQ(s.IsWrite(), true); in TEST()
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| /external/llvm-project/compiler-rt/lib/tsan/tests/unit/ |
| D | tsan_shadow_test.cpp | 27 EXPECT_EQ(s.IsWrite(), true); in TEST()
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| /external/pdfium/third_party/lcms/src/ |
| D | cmsio0.c | 1081 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromIOhandler2THR()
1109 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromFileTHR()
1143 NewIcc -> IsWrite = TRUE; in cmsOpenProfileFromStreamTHR()
1468 if (Icc ->IsWrite) { in cmsCloseProfile()
1470 Icc ->IsWrite = FALSE; // Assure no further writing in cmsCloseProfile()
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| D | lcms2_internal.h | 803 cmsBool IsWrite; member
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