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Searched refs:JALR (Results 1 – 25 of 72) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/
Dreloc-jalr.ll3 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,TAILCALL-32R2
7 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R2,TAILCALL-64R2
11 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R6,TAILCALL-32R6
15 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R6,TAILCALL-64R6
19 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,TAILCALL-32R2
23 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R2,TAILCALL-64R2
27 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-MM,TAILCALL-MM
31 ; RUN: FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-MM,TAILCALL-MM
34 ; RUN: -O0 < %s | FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-32,JALR-32R2,PIC-NOTAILCALL-R2
37 ; RUN: -O0 < %s | FileCheck %s -check-prefixes=ALL,JALR-ALL,JALR-64,JALR-64R2,PIC-NOTAILCALL-R2
[all …]
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Dcopy-fp64.ll17 …; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, impli…
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
Dstore.ll46 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
156 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
266 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
408 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
Dload.ll47 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
186 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
326 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
465 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
605 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
755 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
910 ; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dret.ll32 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
43 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
53 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
63 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
73 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
83 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
93 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
104 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
119 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
135 ; R6-DAG: jr $ra # <MCInst #{{[0-9]+}} JALR
[all …]
Dindirectbr.ll23 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
24 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
29 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
30 ; R6C: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm/test/CodeGen/Mips/
Dlongbranch.ll79 ; In MIPS32R6 JR is an alias to JALR with $rd=0. As everything else remains the
81 ; the opcode of the MachineInst is a JALR.
82 ; O32-R6: JALR
112 ; In MIPS64R6 JR is an alias to JALR with $rd=0. As everything else remains the
114 ; the opcode of the MachineInst is a JALR.
Deh-return32.ll47 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
87 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
Deh-return64.ll48 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
90 ; R6: jr $ra # <MCInst #{{[0-9]+}} JALR
/external/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
89 case Mips::JALR: in isCall()
DMipsInstPrinter.cpp248 case Mips::JALR: in printAlias()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp51 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
81 case Mips::JALR: in isCall()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsNaClELFStreamer.cpp59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
89 case Mips::JALR: in isCall()
DMipsInstPrinter.cpp248 case Mips::JALR: in printAlias()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td384 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
640 def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>;
641 def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>;
642 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;
643 def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;
644 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
645 def : InstAlias<"ret", (JALR X0, X1, 0), 4>;
648 def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>;
649 def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>;
650 def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;
[all …]
/external/llvm-project/lld/ELF/Arch/
DRISCV.cpp46 JALR = 0x67, enumerator
168 write32le(buf + 28, itype(JALR, 0, X_T3, 0)); in writePltHeader()
180 write32le(buf + 8, itype(JALR, X_T1, X_T3, 0)); in writePlt()
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td434 def JALR : RVInstI<0b000, OPC_JALR, (outs GPR:$rd),
702 def : InstAlias<"jr $rs", (JALR X0, GPR:$rs, 0), 3>;
703 def : InstAlias<"jr ${offset}(${rs})", (JALR X0, GPR:$rs, simm12:$offset)>;
704 def : InstAlias<"jalr $rs", (JALR X1, GPR:$rs, 0), 3>;
705 def : InstAlias<"jalr ${offset}(${rs})", (JALR X1, GPR:$rs, simm12:$offset)>;
706 def : InstAlias<"jalr $rd, $rs", (JALR GPR:$rd, GPR:$rs, 0), 2>;
707 def : InstAlias<"ret", (JALR X0, X1, 0), 4>;
710 def : InstAlias<"jr $rs, $offset", (JALR X0, GPR:$rs, simm12:$offset), 0>;
711 def : InstAlias<"jalr $rs, $offset", (JALR X1, GPR:$rs, simm12:$offset), 0>;
712 def : InstAlias<"jalr $rd, $rs, $offset", (JALR GPR:$rd, GPR:$rs, simm12:$offset), 0>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVMCCodeEmitter.cpp130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
133 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/external/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVMCCodeEmitter.cpp148 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); in expandFunctionCall()
151 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); in expandFunctionCall()
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc244 TmpInst.setOpcode(Mips::JALR);
280 TmpInst.setOpcode(Mips::JALR);
573 TmpInst.setOpcode(Mips::JALR);
914 TmpInst.setOpcode(Mips::JALR);
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.cpp253 case Mips::JALR: in printAlias()

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