| /external/llvm-project/llvm/test/CodeGen/ARM/ |
| D | fpoffset_overflow.mir | 48 ; CHECK: KILL $r0
49 ; CHECK: KILL $r1
50 ; CHECK: KILL $r2
51 ; CHECK: KILL $r3
52 ; CHECK: KILL $r4
53 ; CHECK: KILL $r5
54 ; CHECK: KILL $r6
55 ; CHECK: KILL $r7
56 ; CHECK: KILL $r8
57 ; CHECK: KILL $r9
[all …]
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| D | pei-swiftself.mir | 45 KILL $r10
47 KILL $r0
48 KILL $r1
49 KILL $r2
50 KILL $r3
51 KILL $r4
52 KILL $r5
53 KILL $r6
54 KILL $r7
55 KILL $r8
[all …]
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| D | virtregrewriter-subregliveness.mir | 27 ; That copy is being coalesced so we should use a KILL
32 ; CHECK: $r0 = KILL $r0, implicit killed $r0_r1, implicit-def $r0_r1
33 ; CHECK-NEXT: $r1 = KILL $r1, implicit killed $r0_r1
55 ; CHECK: $r0 = KILL $r0, implicit-def $r0_r1
78 ; CHECK: $r0 = KILL $r0, implicit-def $r1, implicit-def $r0_r1
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| /external/llvm-project/llvm/test/CodeGen/Thumb2/ |
| D | mve-stacksplot.mir | 46 ; CHECK: KILL $r0
47 ; CHECK: KILL $r1
48 ; CHECK: KILL $r2
49 ; CHECK: KILL $r3
50 ; CHECK: KILL $r4
51 ; CHECK: KILL $r5
52 ; CHECK: KILL $r6
53 ; CHECK: KILL $r7
54 ; CHECK: KILL $r8
55 ; CHECK: KILL $r9
[all …]
|
| D | fp16-stacksplot.mir | 50 ; CHECK: KILL $r0
51 ; CHECK: KILL $r1
52 ; CHECK: KILL $r2
53 ; CHECK: KILL $r3
54 ; CHECK: KILL $r4
55 ; CHECK: KILL $r5
56 ; CHECK: KILL $r6
57 ; CHECK: KILL $r7
58 ; CHECK: KILL $r8
59 ; CHECK: KILL $r9
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
| D | hazard-recognizer-meta-insts.mir | 16 ; GFX9: $vgpr2 = KILL
20 $vgpr2 = KILL
34 ; GFX9: $vgpr2 = KILL
38 $vgpr2 = KILL
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| D | hazard-kill.mir | 3 # This tests that a KILL isn't considered as a valid instruction for a hazard
14 # GFX90-NEXT: KILL undef renamable $sgpr2
26 dead renamable $sgpr0 = KILL undef renamable $sgpr2
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| D | splitkit-nolivesubranges.mir | 23 …; CHECK: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgp…
28 …; CHECK: KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgp…
36 …KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_…
39 …KILL implicit-def $vcc, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_…
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| D | waitcnt-meta-instructions.mir | 16 ; GCN: KILL $vgpr0
18 KILL $vgpr0
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| D | waitcnt-skip-meta.mir | 19 # CHECK: KILL
25 KILL $sgpr0
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| D | peephole-opt-regseq-removal.mir | 26 ; GCN: KILL [[COPY3]], implicit [[COPY2]]
33 KILL implicit %4, %5
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| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | virtreg-physreg-def-regallocfast.mir | 15 ; CHECK-NOT: $rax = KILL implicit-def dead $rax
16 %0:gr64 = KILL implicit-def dead $rax
17 KILL killed %0
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| D | expand-post-ra-pseudo.mir | 8 ; CHECK-NOT: dead $rax = KILL {{[0-9]+}}
9 ; CHECK: dead $rax = KILL killed $eax
|
| /external/openssh/ |
| D | opensshd.init.in | 9 KILL=@KILL@
46 ${KILL} ${PID}
|
| /external/libcap/cap/ |
| D | names.go | 56 KILL const
348 KILL: "cap_kill",
392 "cap_kill": KILL,
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
|
| /external/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 103 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
114 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
141 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ExpandPostRAPseudos.cpp | 99 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
112 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerSubregToReg()
139 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
156 MI->setDesc(TII->get(TargetOpcode::KILL)); in LowerCopy()
|
| /external/llvm-project/llvm/test/DebugInfo/X86/ |
| D | dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir | 4 ; Test that KILL instructions do not interfere with debug entity history
5 ; liveness ranges. Check that a physical address clobber after KILL still
66 renamable $edi = KILL killed $edi, implicit-def $rdi
73 renamable $eax = KILL killed $eax, implicit-def $rax
|
| D | dbg_entity_calc_ignores_KILL_instruction_at_return.mir | 4 ; Test that KILL instructions no longer terminate the instruction range of a
66 renamable $edi = KILL killed $edi, implicit-def $rdi
73 renamable $eax = KILL killed $eax, implicit-def $rax
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| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | delay-slot-kill.ll | 3 ; Currently, the following IR assembly generates a KILL instruction between
5 ; delay slot filler ignores such KILL instructions by filling the slot of the
|
| /external/llvm/test/CodeGen/Mips/ |
| D | delay-slot-kill.ll | 5 ; Currently, the following IR assembly generates a KILL instruction between
7 ; delay slot filler ignores such KILL instructions by filling the slot of the
|
| /external/llvm-project/llvm/test/DebugInfo/MIR/X86/ |
| D | livedebugvalues-ignores-metaInstructions.mir | 58 renamable $ebx = KILL $ebx
61 renamable $ebx = KILL $ebx
|
| /external/perfetto/ |
| D | traced_perf.rc | 19 # * KILL capability for sending BIONIC_SIGNAL_PROFILER.
29 capabilities KILL DAC_READ_SEARCH
|
| D | heapprofd.rc | 26 capabilities KILL DAC_READ_SEARCH
41 capabilities KILL DAC_READ_SEARCH
|