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Searched refs:Kind_RegDefEarlyClobber (Results 1 – 25 of 25) sorted by relevance

/external/llvm-project/llvm/include/llvm/IR/
DInlineAsm.h233 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r". enumerator
280 return getKind(Flag) == Kind_RegDefEarlyClobber; in isRegDefEarlyClobberKind()
394 case InlineAsm::Kind_RegDefEarlyClobber: in getKindName()
/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/
DInlineAsm.h232 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r". enumerator
279 return getKind(Flag) == Kind_RegDefEarlyClobber; in isRegDefEarlyClobberKind()
/external/llvm/include/llvm/IR/
DInlineAsm.h233 Kind_RegDefEarlyClobber = 3, // Early-clobber output register, "=&r". enumerator
320 return getKind(Flag) == Kind_RegDefEarlyClobber; in isRegDefEarlyClobberKind()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp212 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
230 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp212 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
230 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp213 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
231 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DInlineAsmLowering.cpp408 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber in lowerInlineAsm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DMachineInstr.cpp859 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && in getRegClassConstraint()
1624 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; in print()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp985 case InlineAsm::Kind_RegDefEarlyClobber: in EmitSpecialNode()
DSelectionDAGBuilder.cpp6861 ? InlineAsm::Kind_RegDefEarlyClobber in visitInlineAsm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp1099 case InlineAsm::Kind_RegDefEarlyClobber: in EmitSpecialNode()
DSelectionDAGBuilder.cpp8291 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber in visitInlineAsm()
/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp1196 case InlineAsm::Kind_RegDefEarlyClobber: in EmitSpecialNode()
DSelectionDAGBuilder.cpp8353 OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber in visitInlineAsm()
/external/llvm/lib/Target/X86/
DX86FloatingPoint.cpp1495 case InlineAsm::Kind_RegDefEarlyClobber: in handleSpecialFP()
/external/llvm-project/llvm/lib/Target/X86/
DX86FloatingPoint.cpp1560 case InlineAsm::Kind_RegDefEarlyClobber: in handleSpecialFP()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FloatingPoint.cpp1557 case InlineAsm::Kind_RegDefEarlyClobber: in handleSpecialFP()
/external/llvm-project/llvm/lib/CodeGen/
DMachineInstr.cpp903 InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && in getRegClassConstraint()
/external/llvm/lib/CodeGen/
DMachineInstr.cpp1821 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break; in print()
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp4239 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
4257 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp4946 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
4964 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/llvm-project/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp5332 && Kind != InlineAsm::Kind_RegDefEarlyClobber) in tryInlineAsm()
5350 Kind == InlineAsm::Kind_RegDefEarlyClobber) { in tryInlineAsm()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp658 case InlineAsm::Kind_RegDefEarlyClobber: { in LowerINLINEASM()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp666 case InlineAsm::Kind_RegDefEarlyClobber: { in LowerINLINEASM()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp985 case InlineAsm::Kind_RegDefEarlyClobber: { in LowerINLINEASM()