| /external/llvm-project/llvm/unittests/tools/llvm-exegesis/X86/ |
| D | SnippetGeneratorTest.cpp | 186 TEST_F(SerialSnippetGeneratorTest, LAHF) { in TEST_F() argument
190 const unsigned Opcode = X86::LAHF; in TEST_F()
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| /external/mesa3d/src/gallium/drivers/swr/rasterizer/common/ |
| D | isa.hpp | 93 bool LAHF(void) { return CPU_Rep.f_81_ECX_[0]; } in LAHF() function in InstructionSet
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 559 //LAHF
560 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
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| D | X86ScheduleZnver1.td | 570 //LAHF
571 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
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| D | X86.td | 235 "Support LAHF and SAHF instructions">;
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| D | X86ScheduleBdVer2.td | 518 def : InstRW<[PdWriteLAHF], (instrs LAHF)>;
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| D | X86InstrInfo.td | 1795 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver2.td | 568 //LAHF
569 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
|
| D | X86ScheduleZnver1.td | 573 //LAHF
574 def : InstRW<[WriteMicrocoded], (instrs LAHF)>;
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| D | X86ScheduleBdVer2.td | 518 def : InstRW<[PdWriteLAHF], (instrs LAHF)>;
|
| D | X86.td | 241 "Support LAHF and SAHF instructions in 64-bit mode">;
|
| D | X86InstrInfo.td | 1861 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags
|
| /external/llvm/lib/Target/X86/ |
| D | X86.td | 200 "Support LAHF and SAHF instructions">;
|
| D | X86SchedHaswell.td | 502 // LAHF SAHF.
|
| D | X86InstrInfo.td | 1588 def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", [],
|
| D | X86InstrInfo.cpp | 4573 BuildMI(MBB, MI, DL, get(X86::LAHF)); in copyPhysReg()
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | flags-copy-lowering.mir | 3 # Lower various interesting copy patterns of EFLAGS without using LAHF/SAHF.
|
| /external/mesa3d/src/mesa/x86/ |
| D | assyntax.h | 500 #define LAHF CHOICE(lahf, lahf, lahf) macro
1219 #define LAHF lahf macro
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenSubtargetInfo.inc | 252 …{ "sahf", "Support LAHF and SAHF instructions", X86::FeatureLAHFSAHF, { { { 0x0ULL, 0x0ULL, 0x0ULL…
6633 {DBGFIELD("LAHF") 1, false, false, 3, 1, 3, 1, 0, 0}, // #944
8010 {DBGFIELD("LAHF") 4, false, false, 184, 2, 3, 1, 0, 0}, // #944
9387 {DBGFIELD("LAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #944
10764 {DBGFIELD("LAHF") 1, false, false, 1, 1, 1, 1, 0, 0}, // #944
12141 {DBGFIELD("LAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #944
13518 {DBGFIELD("LAHF") 1, false, false, 1038, 3, 1, 1, 0, 0}, // #944
14895 {DBGFIELD("LAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #944
16272 {DBGFIELD("LAHF") 1, false, false, 188, 1, 1, 1, 0, 0}, // #944
17649 {DBGFIELD("LAHF") 1, false, false, 730, 4, 1, 1, 0, 0}, // #944
[all …]
|
| D | X86GenAsmWriter.inc | 2911 15641U, // LAHF
18162 0U, // LAHF
33413 0U, // LAHF
|
| /external/capstone/arch/X86/ |
| D | X86GenAsmWriter1_reduce.inc | 659 3086U, // LAHF
2377 0U, // LAHF
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| D | X86GenAsmWriter_reduce.inc | 659 5014U, // LAHF
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| D | X86GenAsmWriter1.inc | 1221 10415U, // LAHF
10078 0U, // LAHF
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| D | X86GenAsmWriter.inc | 1221 13001U, // LAHF
10078 0U, // LAHF
|
| /external/llvm-project/clang/docs/ |
| D | UsersManual.rst | 3297 - ``-march=x86-64-v2``: (close to Nehalem) CMPXCHG16B, LAHF-SAHF, POPCNT, SSE3, SSE4.1, SSE4.2, SSS…
|