| /external/libgsm/src/ |
| D | lpc.c | 287 static void Quantization_and_coding P1((LAR),
288 register word * LAR /* [0..7] IN/OUT */
306 temp = GSM_MULT( A, *LAR ); \
310 *LAR = temp>MAC ? MAC - MIC : (temp<MIC ? 0 : temp - MIC); \
311 LAR++;
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| /external/llvm-project/llvm/lib/Transforms/Scalar/ |
| D | LoopPassManager.cpp | 120 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F), in run() local
152 PI.pushBeforeNonSkippedPassCallback([&LAR, &LI](StringRef PassID, Any IR) { in run()
161 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) && in run()
186 PassPA = Pass->run(*L, LAM, LAR, Updater); in run()
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| D | LoopVersioningLICM.cpp | 667 LoopStandardAnalysisResults &LAR, in run() argument
669 AliasAnalysis *AA = &LAR.AA; in run()
670 ScalarEvolution *SE = &LAR.SE; in run()
671 DominatorTree *DT = &LAR.DT; in run()
672 LoopInfo *LI = &LAR.LI; in run()
677 return AM.getResult<LoopAccessAnalysis>(*L, LAR); in run()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Transforms/Scalar/ |
| D | LoopPassManager.h | 301 LoopStandardAnalysisResults LAR = {AM.getResult<AAManager>(F),
348 assert(L->isRecursivelyLCSSAForm(LAR.DT, LI) &&
356 PreservedAnalyses PassPA = Pass.run(*L, LAM, LAR, Updater);
|
| /external/llvm-project/llvm/include/llvm/Transforms/Scalar/ |
| D | LoopVersioningLICM.h | 20 LoopStandardAnalysisResults &LAR, LPMUpdater &U);
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorizationLegality.cpp | 841 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
842 if (LAR) { in canVectorizeMemory()
845 "loop not vectorized: ", *LAR); in canVectorizeMemory()
|
| /external/llvm-project/llvm/lib/Transforms/Vectorize/ |
| D | LoopVectorizationLegality.cpp | 877 const OptimizationRemarkAnalysis *LAR = LAI->getReport(); in canVectorizeMemory() local
878 if (LAR) { in canVectorizeMemory()
881 "loop not vectorized: ", *LAR); in canVectorizeMemory()
|
| /external/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 7584 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in isKnownPredicate() local
7588 if (LAR) { in isKnownPredicate()
7589 const Loop *L = LAR->getLoop(); in isKnownPredicate()
7590 if (isLoopEntryGuardedByCond(L, Pred, LAR->getStart(), RHS) && in isKnownPredicate()
7591 isLoopBackedgeGuardedByCond(L, Pred, LAR->getPostIncExpr(*this), RHS)) { in isKnownPredicate()
7600 if (!LAR) return true; in isKnownPredicate()
8243 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
8246 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
8251 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
8254 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
[all …]
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/ |
| D | core_cm7.h | 1017 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1127 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
|
| D | core_sc300.h | 736 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_cm3.h | 754 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_cm4.h | 815 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/ |
| D | core_cm7.h | 1017 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
1127 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ member
|
| D | core_cm3.h | 754 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_sc300.h | 736 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| D | core_cm4.h | 815 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ member
|
| /external/ImageMagick/PerlMagick/t/reference/write/filter/ |
| D | SigmoidalContrast.miff | 43 ….�2O�^m�FL�1,�- �%�1'�/-�A=�2'�/#�/#�/&�B7�*&�&(�%'�)$�+ �E=����z��Rq�6[�7LAR(m�U��l��n{�a}�a~�g}…
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 9940 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
9943 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
9948 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
9951 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
9954 Less = LAR->getStart(); in computeConstantDifference()
10215 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
10216 if (!LAR) in IsKnownPredicateViaAddRecStart()
10221 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
10223 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
10226 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
[all …]
|
| /external/llvm-project/llvm/lib/Analysis/ |
| D | ScalarEvolution.cpp | 10330 const auto *LAR = cast<SCEVAddRecExpr>(Less); in computeConstantDifference() local
10333 if (LAR->getLoop() != MAR->getLoop()) in computeConstantDifference()
10338 if (!LAR->isAffine() || !MAR->isAffine()) in computeConstantDifference()
10341 if (LAR->getStepRecurrence(*this) != MAR->getStepRecurrence(*this)) in computeConstantDifference()
10344 Less = LAR->getStart(); in computeConstantDifference()
10655 const SCEVAddRecExpr *LAR = dyn_cast<SCEVAddRecExpr>(LHS); in IsKnownPredicateViaAddRecStart() local
10656 if (!LAR) in IsKnownPredicateViaAddRecStart()
10661 if (LAR->getLoop() != RAR->getLoop()) in IsKnownPredicateViaAddRecStart()
10663 if (!LAR->isAffine() || !RAR->isAffine()) in IsKnownPredicateViaAddRecStart()
10666 if (LAR->getStepRecurrence(SE) != RAR->getStepRecurrence(SE)) in IsKnownPredicateViaAddRecStart()
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86ScheduleAtom.td | 432 // LAR
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86SchedBroadwell.td | 1250 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1345 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
|
| D | X86SchedSkylakeClient.td | 901 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1308 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86SchedBroadwell.td | 1253 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1348 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
|
| D | X86SchedHaswell.td | 1436 def: InstRW<[HWWriteResGroup83], (instregex "LAR(16|32|64)rr")>;
1443 def: InstRW<[HWWriteResGroup87], (instregex "LAR(16|32|64)rm",
|
| D | X86SchedSkylakeClient.td | 904 def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
1311 def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
|