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Searched refs:LD2 (Results 1 – 25 of 91) sorted by relevance

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/external/libxaac/decoder/armv8/
Dixheaacd_sbr_imdct_using_fft.s106 LD2 {V0.S, V1.S}[0], [X5], X1
108 LD2 {V4.S, V5.S}[0], [X5], X1
110 LD2 {V2.S, V3.S}[0], [X5], X1
112 LD2 {V6.S, V7.S}[0], [X5], X1
117 LD2 {V0.S, V1.S}[1], [X6] , X1
119 LD2 {V4.S, V5.S}[1], [X6] , X1
121 LD2 {V2.S, V3.S}[1], [X6] , X1
123 LD2 {V6.S, V7.S}[1], [X6], X1
129 LD2 {V0.S, V1.S}[2], [X7] , X1
131 LD2 {V4.S, V5.S}[2], [X7] , X1
[all …]
Dixheaacd_sbr_qmf_analysis32_neon.s147 LD2 {v1.4h, v2.4h}, [x2], #16
164 LD2 {v3.4h, v4.4h}, [x2], #16
171 LD2 {v5.4h, v6.4h}, [x2], #16
178 LD2 {v7.4h, v8.4h}, [x2], #16
186 LD2 {v9.4h, v10.4h}, [x2], #16
196 LD2 {v11.4h, v12.4h}, [x3], #16
205 LD2 {v13.4h, v14.4h}, [x3], #16
209 LD2 {v15.4h, v16.4h}, [x3], #16
219 LD2 {v17.4h, v18.4h}, [x3], #16
226 LD2 {v19.4h, v20.4h}, [x3], #16
[all …]
Dixheaacd_imdct_using_fft.s136 LD2 {v0.S, v1.S}[0], [X5], X1
138 LD2 {v4.S, v5.S}[0], [X5], X1
140 LD2 {v2.S, v3.S}[0], [X5], X1
142 LD2 {v6.S, v7.S}[0], [X5], X1
147 LD2 {v0.S, v1.S}[1], [X6] , X1
149 LD2 {v4.S, v5.S}[1], [X6] , X1
151 LD2 {v2.S, v3.S}[1], [X6] , X1
153 LD2 {v6.S, v7.S}[1], [X6], X1
159 LD2 {v0.S, v1.S}[2], [X7] , X1
161 LD2 {v4.S, v5.S}[2], [X7] , X1
[all …]
Dixheaacd_overlap_add2.s59 LD2 {V0.4H, V1.4H}, [X10], #16
68 LD2 {V6.4H, V7.4H}, [X7], X12
76 LD2 {V2.4H, V3.4H}, [X3], #16
80 LD2 {V8.4H, V9.4H}, [X10], #16
82 LD2 {V10.4H, V11.4H}, [X3], #16
85 LD2 {V14.4H, V15.4H}, [X7], X12
95 LD2 {V0.4H, V1.4H}, [X10], #16
97 LD2 {V2.4H, V3.4H}, [X3], #16
99 LD2 {V6.4H, V7.4H}, [X7], X12
116 LD2 {V8.4H, V9.4H}, [X10], #16
[all …]
Dixheaacd_pre_twiddle.s158 LD2 {v8.h, v9.h}[0], [x3], x6
159 LD2 {v8.h, v9.h}[1], [x3], x6
160 LD2 {v8.h, v9.h}[2], [x3], x6
161 LD2 {v8.h, v9.h}[3], [x3], x6
211 LD2 {v8.h, v9.h}[0], [x3], x6
214 LD2 {v8.h, v9.h}[1], [x3], x6
217 LD2 {v8.h, v9.h}[2], [x3], x6
220 LD2 {v8.h, v9.h}[3], [x3], x6
282 LD2 {v8.h, v9.h}[0], [x3], x6
286 LD2 {v8.h, v9.h}[1], [x3], x6
[all …]
Dixheaacd_post_twiddle.s142 LD2 {v8.h, v9.h}[0], [x2], x6
143 LD2 {v8.h, v9.h}[1], [x2], x6
144 LD2 {v8.h, v9.h}[2], [x2], x6
145 LD2 {v8.h, v9.h}[3], [x2], x6
200 LD2 {v8.h, v9.h}[0], [x2], x6
203 LD2 {v8.h, v9.h}[1], [x2], x6
207 LD2 {v8.h, v9.h}[2], [x2], x6
210 LD2 {v8.h, v9.h}[3], [x2], x6
330 LD2 {v8.h, v9.h}[0], [x2], x6
333 LD2 {v8.h, v9.h}[1], [x2], x6
[all …]
Dixheaacd_post_twiddle_overlap.s314 LD2 { v0.4s, v1.4s}, [x1]
337 LD2 {v8.4h, v9.4h}, [x2]
340 LD2 { v4.4s, v5.4s}, [x8]
365 LD2 { v10.4s, v11.4s}, [x6]
549 LD2 { v28.4s, v29.4s}, [x4]
627 LD2 { v0.4s, v1.4s}, [x1]
657 LD2 { v10.4s, v11.4s}, [x6]
707 LD2 { v4.4s, v5.4s}, [x8]
732 LD2 {v8.4h, v9.4h}, [x2]
965 LD2 { v28.4s, v29.4s}, [x4]
[all …]
Dixheaacd_cos_sin_mod_loop2.s71 LD2 {v0.h, v1.h}[0], [x1], #4
171 LD2 {v0.h, v1.h}[0], [x1], #4
/external/llvm/test/CodeGen/X86/
Dmerge-store-partially-alias-loads.ll21 ; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<LD2[%tmp81](align=1)> [[ENTRYTOKEN]], [[BASEPTR]], und…
24 ; DBGDAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
26 ; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<ST2[%tmp10](align=1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}…
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dmultiple-uses-load-bitcast-select.ll9 ; CHECK-NEXT: [[LD2:%.*]] = load double, double* [[Z1]], align 8
10 ; CHECK-NEXT: [[TMP10:%.*]] = fcmp olt double [[LD1]], [[LD2]]
11 ; CHECK-NEXT: [[TMP121:%.*]] = select i1 [[TMP10]], double [[LD1]], double [[LD2]]
Dload-bitcast-select.ll89 ; CHECK-NEXT: [[LD2:%.*]] = load float, float* [[LOADADDR2:%.*]], align 4
90 ; CHECK-NEXT: [[COND:%.*]] = fcmp ogt float [[LD1]], [[LD2]]
91 ; CHECK-NEXT: [[LD3:%.*]] = select i1 [[COND]], float [[LD1]], float [[LD2]]
Dload-insert-store.ll79 ; CHECK-NEXT: [[LD2:%.*]] = load <16 x i8>, <16 x i8>* [[Q]], align 16
81 ; CHECK-NEXT: [[INS2:%.*]] = insertelement <16 x i8> [[LD2]], i8 [[S]], i32 7
/external/libvpx/libvpx/vp9/common/mips/msa/
Dvp9_mfqe_msa.c31 LD2(src_ptr, src_stride, src0_d, src1_d); in filter_by_weight8x8_msa()
33 LD2(dst_ptr, dst_stride, dst0_d, dst1_d); in filter_by_weight8x8_msa()
37 LD2(src_ptr, src_stride, src0_d, src1_d); in filter_by_weight8x8_msa()
39 LD2((dst_ptr + 2 * dst_stride), dst_stride, dst0_d, dst1_d); in filter_by_weight8x8_msa()
/external/libvpx/libvpx/vp8/common/mips/msa/
Dmfqe_msa.c31 LD2(src_ptr, src_stride, src0_d, src1_d); in filter_by_weight8x8_msa()
33 LD2(dst_ptr, dst_stride, dst0_d, dst1_d); in filter_by_weight8x8_msa()
37 LD2(src_ptr, src_stride, src0_d, src1_d); in filter_by_weight8x8_msa()
39 LD2((dst_ptr + 2 * dst_stride), dst_stride, dst0_d, dst1_d); in filter_by_weight8x8_msa()
/external/llvm-project/llvm/test/CodeGen/X86/
Dmerge-store-partially-alias-loads.ll21 ; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<(load 2 from %ir.tmp81, align 1)> [[ENTRYTOKEN]], [[BA…
25 ; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
26 ; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<(store 2 into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]]…
/external/libhevc/common/arm64/
Dihevc_sao_band_offset_chroma.s309 LD2 {v5.8b, v6.8b},[x4] //vld1q_u8(pu1_src_cpy)
312 LD2 {v13.8b, v14.8b},[x5] //vld1q_u8(pu1_src_cpy)
315 LD2 {v17.8b, v18.8b},[x6] //vld1q_u8(pu1_src_cpy)
318 LD2 {v21.8b, v22.8b},[x7] //vld1q_u8(pu1_src_cpy)
363 LD2 {v5.8b, v6.8b},[x4] //vld1q_u8(pu1_src_cpy)
367 LD2 {v13.8b, v14.8b},[x5] //vld1q_u8(pu1_src_cpy)
370 LD2 {v17.8b, v18.8b},[x6] //vld1q_u8(pu1_src_cpy)
379 LD2 {v21.8b, v22.8b},[x7] //vld1q_u8(pu1_src_cpy)
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-load-1.ll2 …= load 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](align=8), sext from v2i8>", 0x16c5890, 0x16f76e0…
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dunal-altivec.ll38 ; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
Dbotheightreduce.mir39 ; CHECK: [[LD2:%[0-9]+]]:g8rc = LD 8, [[ADDI8_]] :: (load 8)
46 ; CHECK: [[MADDLD8_:%[0-9]+]]:g8rc = MADDLD8 [[MULLD6]], [[LD2]], [[MADDLD8_]]
/external/llvm/test/CodeGen/PowerPC/
Dunal-altivec.ll41 ; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]], [[C15]]
44 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dcluster_stores.ll22 ; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8
36 ; GCN-NEXT: flat_store_dword v[{{[0-9:]+}}], [[LD2]] offset:8
67 ; GCN-NEXT: flat_load_dword [[LD2:v[0-9]+]], v[{{[0-9:]+}}] offset:8
81 ; GCN: v_add_u32_e32 [[ST2:v[0-9]+]], 1, [[LD2]]
/external/libvpx/libvpx/vp8/encoder/mips/msa/
Dtemporal_filter_msa.c148 LD2(frame1_ptr, stride, f0, f1); in temporal_filter_apply_8size_msa()
150 LD2(frame2_ptr, 8, f2, f3); in temporal_filter_apply_8size_msa()
152 LD2(frame1_ptr, stride, f4, f5); in temporal_filter_apply_8size_msa()
154 LD2(frame2_ptr, 8, f6, f7); in temporal_filter_apply_8size_msa()
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dproxy-reg-erasure-ptx.ll140 …; PTX-DAG: ld.param.v4.b32 {[[LD0:%r[0-9]+]], [[LD1:%r[0-9]+]], [[LD2:%r[0-9]+]], [[LD3:%r[0-9]+]]…
145 ; PTX-WITHOUT-DAG: mov.b32 [[PROXY2:%r[0-9]+]], [[LD2]];
148 ; PTX-WITH-DAG: st.param.v4.b32 [func_retval0+0], {[[LD0]], [[LD1]], [[LD2]], [[LD3]]};
/external/llvm-project/llvm/test/CodeGen/Hexagon/vect/
Dvect-load-1.ll3 ; Used to fail with "Cannot select: v2i32,ch = load 0x16c5890, 0x16f76e0, 0x16f76e0<LD2[undef](alig…
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dcall-translator-ios.ll60 ; CHECK: [[LD2:%[0-9]+]]:_(s64) = G_LOAD %3(p0) :: (load 8 from %ir.ptr + 8)
68 ; CHECK: G_STORE [[LD2]](s64), [[ADDR]](p0) :: (store 8 into stack + 8, align 1)

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