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Searched refs:LD_W (Results 1 – 25 of 33) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfloating_point_vec_arithmetic_operations.mir33 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
34 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
35 ; P5600: [[FADD_W:%[0-9]+]]:msa128w = FADD_W [[LD_W]], [[LD_W1]]
93 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
94 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
95 ; P5600: [[FSUB_W:%[0-9]+]]:msa128w = FSUB_W [[LD_W]], [[LD_W1]]
153 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
154 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
155 ; P5600: [[FMUL_W:%[0-9]+]]:msa128w = FMUL_W [[LD_W]], [[LD_W1]]
213 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
[all …]
Dload_store_vec.mir75 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
76 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
123 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
124 ; P5600: ST_W [[LD_W]], [[COPY]], 0 :: (store 16 into %ir.a)
Drem_and_div_vec.mir101 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
102 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
103 ; P5600: [[DIV_S_W:%[0-9]+]]:msa128w = DIV_S_W [[LD_W]], [[LD_W1]]
221 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
222 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
223 ; P5600: [[MOD_S_W:%[0-9]+]]:msa128w = MOD_S_W [[LD_W]], [[LD_W1]]
341 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
342 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
343 ; P5600: [[DIV_U_W:%[0-9]+]]:msa128w = DIV_U_W [[LD_W]], [[LD_W1]]
461 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
[all …]
Dfsqrt_vec.mir23 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
24 ; P5600: [[FSQRT_W:%[0-9]+]]:msa128w = FSQRT_W [[LD_W]]
Dfabs_vec.mir23 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
24 ; P5600: [[FABS_W:%[0-9]+]]:msa128w = FABS_W [[LD_W]]
Dsub_vec.mir86 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
87 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
88 ; P5600: [[SUBV_W:%[0-9]+]]:msa128w = SUBV_W [[LD_W1]], [[LD_W]]
Dmul_vec.mir86 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
87 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
88 ; P5600: [[MULV_W:%[0-9]+]]:msa128w = MULV_W [[LD_W1]], [[LD_W]]
Dadd_vec.mir86 ; P5600: [[LD_W:%[0-9]+]]:msa128w = LD_W [[COPY]], 0 :: (load 16 from %ir.a)
87 ; P5600: [[LD_W1:%[0-9]+]]:msa128w = LD_W [[COPY1]], 0 :: (load 16 from %ir.b)
88 ; P5600: [[ADDV_W:%[0-9]+]]:msa128w = ADDV_W [[LD_W1]], [[LD_W]]
/external/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
91 case Mips::LD_W: in getLoadStoreOffsetAlign()
DMipsSEInstrInfo.cpp288 Opc = Mips::LD_W; in loadRegFromStack()
DMipsMSAInstrInfo.td3216 def LD_W: LD_W_ENC, LD_W_DESC;
3527 def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
134 case Mips::LD_W: in getLoadStoreOffsetAlign()
DMipsInstructionSelector.cpp239 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
DMipsSEInstrInfo.cpp357 Opc = Mips::LD_W; in loadRegFromStack()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSERegisterInfo.cpp74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
134 case Mips::LD_W: in getLoadStoreOffsetAlign()
DMipsInstructionSelector.cpp245 return isStore ? Mips::ST_W : Mips::LD_W; in selectLoadStoreOpCode()
DMipsSEInstrInfo.cpp357 Opc = Mips::LD_W; in loadRegFromStack()
DMipsMSAInstrInfo.td3276 def LD_W: LD_W_ENC, LD_W_DESC;
3587 def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>;
/external/webp/src/dsp/
Dmsa_macro.h56 #define LD_W(RTYPE, psrc) *((RTYPE*)(psrc)) macro
57 #define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
58 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
271 out0 = LD_W(RTYPE, psrc); \
272 out1 = LD_W(RTYPE, psrc + stride); \
279 out2 = LD_W(RTYPE, psrc + 2 * stride); \
/external/libvpx/libvpx/vp8/common/mips/msa/
Dvp8_macros_msa.h27 #define LD_W(RTYPE, psrc) *((const RTYPE *)(psrc)) macro
28 #define LD_UW(...) LD_W(v4u32, __VA_ARGS__)
29 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
/external/libaom/libaom/aom_dsp/mips/
Dmacros_msa.h29 #define LD_W(RTYPE, psrc) *((const RTYPE *)(psrc)) macro
30 #define LD_SW(...) LD_W(v4i32, __VA_ARGS__)
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1494 case Mips::LD_W: in DecodeMSA128Mem()
/external/llvm-project/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1737 case Mips::LD_W: in DecodeMSA128Mem()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp1737 case Mips::LD_W: in DecodeMSA128Mem()
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc965 58744179U, // LD_W
2754 0U, // LD_W

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