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/external/mesa3d/src/mesa/drivers/dri/i965/
Dhsw_queryobj.c41 MI_MATH_ALU2(LOAD, SRCA, R0), in mult_gpr0_by_80()
42 MI_MATH_ALU2(LOAD, SRCB, R0), in mult_gpr0_by_80()
45 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
46 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
49 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
50 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
53 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
54 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
58 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
59 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
[all …]
Dhsw_sol.c107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
108 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
113 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
129 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
130 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
138 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
139 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
142 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
143 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
/external/llvm-project/lld/test/ELF/
Dseparate-segments.s8 # NONE: LOAD 0x000000 0x0000000000000000 0x0000000000000000 0x000245 0x000245 R 0x1000
9 # NONE-NEXT: LOAD 0x000248 0x0000000000001248 0x0000000000001248 0x000001 0x000001 R E 0x1000
10 # NONE-NEXT: LOAD 0x000250 0x0000000000002250 0x0000000000002250 0x000090 0x000090 RW 0x1000
11 # NONE-NEXT: LOAD 0x0002e0 0x00000000000032e0 0x00000000000032e0 0x000001 0x000001 RW 0x1000
17 # CODE: LOAD 0x000000 0x0000000000000000 0x0000000000000000 0x000245 0x000245 R 0x1000
18 # CODE-NEXT: LOAD 0x001000 0x0000000000001000 0x0000000000001000 0x000001 0x000001 R E 0x1000
19 # CODE-NEXT: LOAD 0x002000 0x0000000000002000 0x0000000000002000 0x000090 0x000090 RW 0x1000
20 # CODE-NEXT: LOAD 0x002090 0x0000000000003090 0x0000000000003090 0x000001 0x000001 RW 0x1000
25 # ALL: LOAD 0x000000 0x0000000000000000 0x0000000000000000 0x000245 0x000245 R 0x1000
26 # ALL-NEXT: LOAD 0x001000 0x0000000000001000 0x0000000000001000 0x000001 0x000001 R E 0x1000
[all …]
/external/llvm-project/llvm/test/tools/llvm-objcopy/MachO/
Dinstall-name-tool-change.test7 # RUN: llvm-install-name-tool -change /usr/dylib/LOAD /usr/long/long/dylib/LOAD %t.copy
10 # CHANGE: name /usr/long/long/dylib/LOAD
16 # RUN: -change /usr/dylib/LOAD /usr/sh/LOAD %t.copy
19 # CHANGE-MULTIPLE: name /usr/sh/LOAD
24 # RUN: llvm-install-name-tool -change /usr/dylib/LOAD /usr/LOAD \
25 # RUN: -change /usr/dylib/LOAD /usr/XXXX %t.copy
28 # CHANGE-REPEAT: name /usr/LOAD
33 # RUN: llvm-install-name-tool -change /usr/dylib/LOAD /usr/XX/LOAD \
34 # RUN: -change /usr/XX/LOAD /usr/YY/LOAD %t.copy
37 # CHANGE-CHAIN: name /usr/XX/LOAD
[all …]
/external/llvm-project/llvm/test/Instrumentation/HeapProfiler/
Dmasked-load-store.ll2 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL
6 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL
134 ;;;;;;;;;;;;;;;; LOAD
143 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
144 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
145 ; LOAD: call void @__memprof_load(i64 [[PGEP0]])
146 ; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
147 ; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
148 ; LOAD: call void @__memprof_load(i64 [[PGEP1]])
149 ; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/legalizer/
Dload_4_unaligned.mir72 …; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align…
73 ; MIPS32: $f0 = COPY [[LOAD]](s32)
77 …; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_ali…
78 ; MIPS32R6: $f0 = COPY [[LOAD]](s32)
94 …; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align…
95 ; MIPS32: $f0 = COPY [[LOAD]](s32)
99 …; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_ali…
100 ; MIPS32R6: $f0 = COPY [[LOAD]](s32)
116 …; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_align…
117 ; MIPS32: $f0 = COPY [[LOAD]](s32)
[all …]
Dload_split_because_of_memsize_or_align220 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
222 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
229 ; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
231 ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
253 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
255 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
262 ; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
264 ; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
286 ; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
288 ; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dinst-select-load-atomic-local.mir55 … ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load seq_cst 4, addrspace 3)
56 ; GFX6: $vgpr0 = COPY [[LOAD]](<2 x s16>)
61 … ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load seq_cst 4, addrspace 3)
62 ; GFX7: $vgpr0 = COPY [[LOAD]](<2 x s16>)
66 … ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load seq_cst 4, addrspace 3)
67 ; GFX9: $vgpr0 = COPY [[LOAD]](<2 x s16>)
89 ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p3) :: (load seq_cst 4, addrspace 3)
90 ; GFX6: $vgpr0 = COPY [[LOAD]](p3)
95 ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p3) :: (load seq_cst 4, addrspace 3)
96 ; GFX7: $vgpr0 = COPY [[LOAD]](p3)
[all …]
Dinst-select-load-global.s96.mir68 ; GFX7: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
69 ; GFX7: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
73 …; GFX7-FLAT: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
74 ; GFX7-FLAT: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
78 ; GFX8: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
79 ; GFX8: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
83 ; GFX9: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
84 ; GFX9: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
88 ; GFX10: [[LOAD:%[0-9]+]]:vreg_96(s96) = G_LOAD [[COPY]](p1) :: (load 12, align 4, addrspace 1)
89 ; GFX10: $vgpr0_vgpr1_vgpr2 = COPY [[LOAD]](s96)
[all …]
Dinst-select-load-atomic-flat.mir46 ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
47 ; GFX7: $vgpr0 = COPY [[LOAD]](<2 x s16>)
51 ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
52 ; GFX9: $vgpr0 = COPY [[LOAD]](<2 x s16>)
73 ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
74 ; GFX7: $vgpr0 = COPY [[LOAD]](p3)
78 ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p0) :: (load seq_cst 4)
79 ; GFX9: $vgpr0 = COPY [[LOAD]](p3)
127 ; GFX7: [[LOAD:%[0-9]+]]:vreg_64(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load seq_cst 8)
128 ; GFX7: $vgpr0_vgpr1 = COPY [[LOAD]](<2 x s32>)
[all …]
Dinst-select-load-atomic-global.mir68 … ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)
69 ; GFX6: $vgpr0 = COPY [[LOAD]](<2 x s16>)
73 … ; GFX7: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)
74 ; GFX7: $vgpr0 = COPY [[LOAD]](<2 x s16>)
78 …; GFX7-FLAT: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspa…
79 ; GFX7-FLAT: $vgpr0 = COPY [[LOAD]](<2 x s16>)
83 … ; GFX9: [[LOAD:%[0-9]+]]:vgpr_32(<2 x s16>) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)
84 ; GFX9: $vgpr0 = COPY [[LOAD]](<2 x s16>)
105 ; GFX6: [[LOAD:%[0-9]+]]:vgpr_32(p3) = G_LOAD [[COPY]](p1) :: (load seq_cst 4, addrspace 1)
106 ; GFX6: $vgpr0 = COPY [[LOAD]](p3)
[all …]
Dlegalize-sextload-flat.mir16 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
17 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
36 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
37 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
57 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
58 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
80 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
81 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
102 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
103 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
[all …]
Dlegalize-zextload-flat.mir16 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
18 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
37 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
39 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
59 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
61 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
83 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 1)
85 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
106 ; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 2)
108 ; VI: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
[all …]
/external/llvm-project/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll2 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL
4 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL
10 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL
12 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL
156 ;;;;;;;;;;;;;;;; LOAD
165 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
166 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
167 ; LOAD: call void @__asan_load4(i64 [[PGEP0]])
168 ; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
169 ; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
[all …]
/external/llvm-project/lld/test/wasm/
Dload-undefined.test12 ; RUN: obj2yaml %t2.wasm | FileCheck %s -check-prefix=NO-LOAD
29 ; NO-LOAD: Name: name
30 ; NO-LOAD-NEXT: FunctionNames:
31 ; NO-LOAD-NEXT: - Index: 0
32 ; NO-LOAD-NEXT: Name: __wasm_call_ctors
33 ; NO-LOAD-NEXT: - Index: 1
34 ; NO-LOAD-NEXT: Name: _start
35 ; NO-LOAD-NEXT: - Index: 2
36 ; NO-LOAD-NEXT: Name: ret64
37 ; NO-LOAD-NEXT: GlobalNames:
[all …]
/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
[all …]
/external/llvm-project/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
[all …]
/external/llvm-project/llvm/test/Transforms/GVN/
Dequality-assume.ll6 ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[P:%.*]]
7 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[LOAD]], [[V:%.*]]
19 ; CHECK-NEXT: [[LOAD:%.*]] = load i32, i32* [[P:%.*]]
20 ; CHECK-NEXT: [[C:%.*]] = icmp eq i32 [[LOAD]], [[V:%.*]]
33 ; CHECK-NEXT: [[LOAD:%.*]] = load float, float* [[P:%.*]]
34 ; CHECK-NEXT: [[C:%.*]] = fcmp oeq float [[LOAD]], [[V:%.*]]
36 ; CHECK-NEXT: ret float [[LOAD]]
47 ; CHECK-NEXT: [[LOAD:%.*]] = load float, float* [[P:%.*]]
48 ; CHECK-NEXT: [[C:%.*]] = fcmp ueq float [[LOAD]], [[V:%.*]]
50 ; CHECK-NEXT: ret float [[LOAD]]
[all …]
/external/llvm-project/clang/test/CodeGenObjC/
Darc-blocks-exceptions.m18 // CHECK-NEXT: [[LOAD:%.*]] = load i1, i1* [[CLEANUP_COND]]
19 // CHECK-NEXT: br i1 [[LOAD]], label %[[END_OF_SCOPE_LAB:.*]], label
22 // CHECK-NEXT: [[LOAD:%.*]] = load i8**, i8*** [[CLEANUP_SAVE]]
23 // CHECK-NEXT: call void @llvm.objc.destroyWeak(i8** [[LOAD]])
28 // CHECK: [[LOAD:%.*]] = load i1, i1* [[CLEANUP_COND]]
29 // CHECK-NEXT: br i1 [[LOAD]], label %[[EH_CLEANUP_LAB:.*]], label
32 // CHECK-NEXT: [[LOAD:%.*]] = load i8**, i8*** [[CLEANUP_SAVE]]
33 // CHECK-NEXT: call void @llvm.objc.destroyWeak(i8** [[LOAD]])
/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/regbankselect/
Dload_4_unaligned.mir38 …; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_al…
39 ; MIPS32: $f0 = COPY [[LOAD]](s32)
43 …; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_…
44 ; MIPS32R6: $f0 = COPY [[LOAD]](s32)
61 …; MIPS32: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_al…
62 ; MIPS32: $f0 = COPY [[LOAD]](s32)
66 …; MIPS32R6: [[LOAD:%[0-9]+]]:fprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @float_…
67 ; MIPS32R6: $f0 = COPY [[LOAD]](s32)
84 …; MIPS32: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i32_alig…
85 ; MIPS32: $v0 = COPY [[LOAD]](s32)
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dirtranslator-load-metadata.ll9 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load 4 from %ir.ptr)
10 ; CHECK: $w0 = COPY [[LOAD]](s32)
21 …; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load 4 from %ir.pt…
22 ; CHECK: $w0 = COPY [[LOAD]](s32)
33 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable load 4 from %ir.ptr)
34 ; CHECK: $w0 = COPY [[LOAD]](s32)
45 …; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable invariant load 4 from…
46 ; CHECK: $w0 = COPY [[LOAD]](s32)
57 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load 4 from %ir.ptr)
58 ; CHECK: $w0 = COPY [[LOAD]](s32)
[all …]
/external/llvm-project/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
Dptrmask.ll10 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[MASKED]], align 1
11 ; CHECK-NEXT: ret i8 [[LOAD]]
23 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[MASKED]], align 1
24 ; CHECK-NEXT: ret i8 [[LOAD]]
36 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8* [[MASKED]], align 1
37 ; CHECK-NEXT: ret i8 [[LOAD]]
48 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8 addrspace(1)* [[TMP1]], align 1
49 ; CHECK-NEXT: ret i8 [[LOAD]]
60 ; CHECK-NEXT: [[LOAD:%.*]] = load i8, i8 addrspace(999)* [[TMP1]], align 1
61 ; CHECK-NEXT: ret i8 [[LOAD]]
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dtrunc-cmp-constant.ll5 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
6 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
20 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
21 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
46 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
58 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
82 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
83 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
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