| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 67 FUNCTION(lrint, 1, 1, experimental_constrained_lrint, LRINT)
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 643 LROUND, LLROUND, LRINT, LLRINT, enumerator
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| /external/llvm-project/llvm/include/llvm/IR/ |
| D | ConstrainedOps.def | 81 DAG_FUNCTION(lrint, 1, 1, experimental_constrained_lrint, LRINT)
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 815 LRINT, enumerator
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 316 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 394 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
395 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 349 case ISD::LRINT: return "lrint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 789 case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break; in SoftenFloatOperand()
1668 case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break; in ExpandFloatOperand()
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| D | LegalizeDAG.cpp | 1007 case ISD::LRINT: in LegalizeOp()
4086 case ISD::LRINT: in ConvertNodeToLibcall()
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| D | SelectionDAGBuilder.cpp | 6210 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in visitIntrinsicCall()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 361 case ISD::LRINT: return "lrint"; in getOperationName()
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| D | LegalizeFloatTypes.cpp | 827 case ISD::LRINT: Res = SoftenFloatOp_LRINT(N); break; in SoftenFloatOperand()
1758 case ISD::LRINT: Res = ExpandFloatOp_LRINT(N); break; in ExpandFloatOperand()
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| D | LegalizeDAG.cpp | 1006 case ISD::LRINT: in LegalizeOp()
4264 case ISD::LRINT: in ConvertNodeToLibcall()
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| D | SelectionDAGBuilder.cpp | 6098 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in visitIntrinsicCall()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCTargetTransformInfo.cpp | 475 case Intrinsic::lrint: Opcode = ISD::LRINT; break; in mightUseCTR()
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| D | PPCISelLowering.cpp | 496 setOperationAction(ISD::LRINT, MVT::f64, Legal); in PPCTargetLowering()
497 setOperationAction(ISD::LRINT, MVT::f32, Legal); in PPCTargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 758 setOperationAction(ISD::LRINT, VT, Expand); in initActions()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 879 setOperationAction(ISD::LRINT, VT, Expand); in initActions()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 471 def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
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| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 478 def lrint : SDNode<"ISD::LRINT" , SDTFPToIntOp>;
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 271 setOperationAction(ISD::LRINT, MVT::f32, Custom); in X86TargetLowering()
272 setOperationAction(ISD::LRINT, MVT::f64, Custom); in X86TargetLowering()
277 setOperationAction(ISD::LRINT, MVT::i64, Custom); in X86TargetLowering()
675 setOperationAction(ISD::LRINT, MVT::f80, Custom); in X86TargetLowering()
29775 case ISD::LRINT: in LowerOperation()
30309 case ISD::LRINT: in ReplaceNodeResults()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 519 setOperationAction(ISD::LRINT, Ty, Legal); in AArch64TargetLowering()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 651 setOperationAction(ISD::LRINT, Ty, Legal); in AArch64TargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 666 setOperationAction(ISD::LRINT, MVT::f80, Expand); in X86TargetLowering()
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenDAGISel.inc | 19090 /* 48347*/ /*SwitchOpcode*/ 54, TARGET_VAL(ISD::LRINT),// ->48404
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