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Searched refs:LSHR (Results 1 – 25 of 212) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
D	inst-select-lshr.v2s16.mir	23 ; GFX6: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>) 24 ; GFX6: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>) 28 ; GFX7: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>) 29 ; GFX7: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>) 33 ; GFX8: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>) 34 ; GFX8: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>) 38 ; GFX9: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>) 39 ; GFX9: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>) 43 ; GFX10: [[LSHR:%[0-9]+]]:sgpr(<2 x s16>) = G_LSHR [[COPY]], [[COPY1]](<2 x s16>) 44 ; GFX10: S_ENDPGM 0, implicit [[LSHR]](<2 x s16>) [all …]
D	regbankselect-lshr.mir	15 ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[COPY]], [[COPY1]](s32) 16 ; CHECK: S_ENDPGM 0, implicit [[LSHR]](s32) 34 ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY2]], [[COPY1]](s32) 35 ; CHECK: S_ENDPGM 0, implicit [[LSHR]](s32) 53 ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY]], [[COPY2]](s32) 54 ; CHECK: S_ENDPGM 0, implicit [[LSHR]](s32) 71 ; CHECK: [[LSHR:%[0-9]+]]:vgpr(s32) = G_LSHR [[COPY]], [[COPY1]](s32) 72 ; CHECK: S_ENDPGM 0, implicit [[LSHR]](s32) 93 ; CHECK: [[LSHR:%[0-9]+]]:sgpr(s32) = G_LSHR [[ZEXT]], [[ZEXT1]](s32) 94 ; CHECK: [[TRUNC2:%[0-9]+]]:sgpr(s16) = G_TRUNC [[LSHR]](s32) [all …]
D	inst-select-lshr.s16.mir	35 ; GFX8: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16) 36 ; GFX8: S_ENDPGM 0, implicit [[LSHR]](s16) 42 ; GFX9: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16) 43 ; GFX9: S_ENDPGM 0, implicit [[LSHR]](s16) 49 ; GFX10: [[LSHR:%[0-9]+]]:sgpr(s16) = G_LSHR [[TRUNC]], [[TRUNC1]](s16) 50 ; GFX10: S_ENDPGM 0, implicit [[LSHR]](s16) 103 ; GFX8: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32) 104 ; GFX8: S_ENDPGM 0, implicit [[LSHR]](s16) 109 ; GFX9: [[LSHR:%[0-9]+]]:vgpr(s16) = G_LSHR [[TRUNC]], [[COPY1]](s32) 110 ; GFX9: S_ENDPGM 0, implicit [[LSHR]](s16) [all …]
D	combine-lshr-narrow.mir	56 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32) 58 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LSHR]](s32), [[C1]](s32) 77 ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32) 78 ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64) 97 ; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32) 99 ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LSHR]](s32), [[C1]](s32) 118 ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32) 119 ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64) 137 ; CHECK: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32) 138 ; CHECK: $vgpr0_vgpr1 = COPY [[LSHR]](s64) [all …]
D	legalize-lshr.mir	15 ; SI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32) 16 ; SI: $vgpr0 = COPY [[LSHR]](s32) 20 ; VI: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32) 21 ; VI: $vgpr0 = COPY [[LSHR]](s32) 25 ; GFX9: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[COPY1]](s32) 26 ; GFX9: $vgpr0 = COPY [[LSHR]](s32) 42 ; SI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32) 43 ; SI: $vgpr0_vgpr1 = COPY [[LSHR]](s64) 48 ; VI: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[TRUNC]](s32) 49 ; VI: $vgpr0_vgpr1 = COPY [[LSHR]](s64) [all …]
D	legalize-shuffle-vector.s16.mir	50 ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 52 ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 87 ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 90 ; GFX8: [[COPY3:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 124 ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 129 ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 165 ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C1]](s32) 169 ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) 204 ; GFX8: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) 208 ; GFX8: [[COPY2:%[0-9]+]]:_(s32) = COPY [[LSHR]](s32) [all …]
D	legalize-ushlsat.mir	22 ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32) 24 ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR]] 39 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SHL1]], [[AND]](s16) 41 ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s16), [[LSHR]] 56 ; GFX9: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SHL1]], [[AND]](s16) 58 ; GFX9: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s16), [[LSHR]] 88 ; GFX6: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[SHL1]], [[AND]](s32) 90 ; GFX6: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s32), [[LSHR]] 105 ; GFX8: [[LSHR:%[0-9]+]]:_(s16) = G_LSHR [[SHL1]], [[AND]](s16) 107 ; GFX8: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SHL]](s16), [[LSHR]] [all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
D	lshr-and-negC-icmpeq-zero.ll	12 ; CHECK-NEXT: [[LSHR:%.]] = lshr i8 [[X:%.]], [[Y:%.]] 13 ; CHECK-NEXT: [[R:%.]] = icmp ult i8 [[LSHR]], 4 24 ; CHECK-NEXT: [[LSHR:%.]] = lshr i16 [[X:%.]], [[Y:%.]] 25 ; CHECK-NEXT: [[R:%.]] = icmp ult i16 [[LSHR]], 128 36 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 [[X:%.]], [[Y:%.]] 37 ; CHECK-NEXT: [[R:%.]] = icmp ult i32 [[LSHR]], 262144 48 ; CHECK-NEXT: [[LSHR:%.]] = lshr i64 [[X:%.]], [[Y:%.]] 49 ; CHECK-NEXT: [[R:%.]] = icmp ult i64 [[LSHR]], 8589934592 60 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 [[X:%.]], [[Y:%.]] 61 ; CHECK-NEXT: [[R:%.]] = icmp ugt i32 [[LSHR]], 262143 [all …]
D	signbit-lshr-and-icmpeq-zero.ll	11 ; CHECK-NEXT: [[LSHR:%.]] = lshr i8 -128, [[Y:%.]] 12 ; CHECK-NEXT: [[AND:%.]] = and i8 [[LSHR]], [[X:%.]] 24 ; CHECK-NEXT: [[LSHR:%.]] = lshr i16 -32768, [[Y:%.]] 25 ; CHECK-NEXT: [[AND:%.]] = and i16 [[LSHR]], [[X:%.]] 37 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 -2147483648, [[Y:%.]] 38 ; CHECK-NEXT: [[AND:%.]] = and i32 [[LSHR]], [[X:%.]] 50 ; CHECK-NEXT: [[LSHR:%.]] = lshr i64 -9223372036854775808, [[Y:%.]] 51 ; CHECK-NEXT: [[AND:%.]] = and i64 [[LSHR]], [[X:%.]] 63 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 -2147483648, [[Y:%.]] 64 ; CHECK-NEXT: [[AND:%.]] = and i32 [[LSHR]], [[X:%.]] [all …]
D	lshr-and-signbit-icmpeq-zero.ll	12 ; CHECK-NEXT: [[LSHR:%.]] = lshr i8 [[X:%.]], [[Y:%.]] 13 ; CHECK-NEXT: [[R:%.]] = icmp sgt i8 [[LSHR]], -1 24 ; CHECK-NEXT: [[LSHR:%.]] = lshr i16 [[X:%.]], [[Y:%.]] 25 ; CHECK-NEXT: [[R:%.]] = icmp sgt i16 [[LSHR]], -1 36 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 [[X:%.]], [[Y:%.]] 37 ; CHECK-NEXT: [[R:%.]] = icmp sgt i32 [[LSHR]], -1 48 ; CHECK-NEXT: [[LSHR:%.]] = lshr i64 [[X:%.]], [[Y:%.]] 49 ; CHECK-NEXT: [[R:%.]] = icmp sgt i64 [[LSHR]], -1 60 ; CHECK-NEXT: [[LSHR:%.]] = lshr i32 [[X:%.]], [[Y:%.]] 61 ; CHECK-NEXT: [[R:%.]] = icmp slt i32 [[LSHR]], 0 [all …]
/external/llvm/test/CodeGen/AMDGPU/
D	srl.ll	10 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 49 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 50 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 51 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 52 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 70 ; EG-DAG: LSHR {{\? }}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 72 ; EG-DAG: LSHR {{\? }}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS\|[[SHIFT]]\|PV\.[XYZW]}} 75 ; EG-DAG: LSHR {{\? }}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], [[SHIFT]] [all …]
D	fp_to_sint.ll	`56 ; EG-DAG: LSHR 66 ; EG-DAG: LSHR 67 ; EG-DAG: LSHR 88 ; EG-DAG: LSHR 98 ; EG-DAG: LSHR 99 ; EG-DAG: LSHR 109 ; EG-DAG: LSHR 119 ; EG-DAG: LSHR 120 ; EG-DAG: LSHR 139 ; EG-DAG: LSHR [all …]`
D	fp_to_uint.ll	`47 ; EG-DAG: LSHR 57 ; EG-DAG: LSHR 58 ; EG-DAG: LSHR 77 ; EG-DAG: LSHR 87 ; EG-DAG: LSHR 88 ; EG-DAG: LSHR 98 ; EG-DAG: LSHR 108 ; EG-DAG: LSHR 109 ; EG-DAG: LSHR 128 ; EG-DAG: LSHR [all …]`
D	set-dx10.ll	`8 ; CHECK: LSHR 22 ; CHECK: LSHR 34 ; CHECK: LSHR 48 ; CHECK: LSHR 60 ; CHECK: LSHR 74 ; CHECK: LSHR 86 ; CHECK: LSHR 100 ; CHECK: LSHR 112 ; CHECK: LSHR 126 ; CHECK: LSHR [all …]`
D	unsupported-cc.ll	`6 ; CHECK: LSHR 18 ; CHECK: LSHR 33 ; CHECK-NEXT: LSHR * 43 ; CHECK: LSHR 55 ; CHECK: LSHR 67 ; CHECK: LSHR 79 ; CHECK: LSHR 94 ; CHECK-NEXT: LSHR * 104 ; CHECK: LSHR 116 ; CHECK: LSHR`
D	image-resource-id.ll	`8 ; EG-NEXT: LSHR 22 ; EG-NEXT: LSHR 38 ; EG-NEXT: LSHR 52 ; EG-NEXT: LSHR 68 ; EG-NEXT: LSHR 83 ; EG-NEXT: LSHR 98 ; EG-NEXT: LSHR 113 ; EG-NEXT: LSHR 130 ; EG-NEXT: LSHR 145 ; EG-NEXT: LSHR [all …]`
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
D	srl.ll	10 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 27 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 28 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 49 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 50 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 51 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 52 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 70 ; EG-DAG: LSHR {{\? }}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]] 72 ; EG-DAG: LSHR {{\? }}[[HISM:T[0-9]+\.[XYZW]]], [[OPHI]], {{PS\|[[SHIFT]]\|PV\.[XYZW]}} 75 ; EG-DAG: LSHR {{\? }}[[LOBIG:T[0-9]+\.[XYZW]]], [[OPHI]], [[SHIFT]] [all …]
D	fp_to_uint.ll	`49 ; EG-DAG: LSHR 59 ; EG-DAG: LSHR 60 ; EG-DAG: LSHR 79 ; EG-DAG: LSHR 89 ; EG-DAG: LSHR 90 ; EG-DAG: LSHR 100 ; EG-DAG: LSHR 110 ; EG-DAG: LSHR 111 ; EG-DAG: LSHR 130 ; EG-DAG: LSHR [all …]`
D	fp_to_sint.ll	`56 ; EG-DAG: LSHR 66 ; EG-DAG: LSHR 67 ; EG-DAG: LSHR 88 ; EG-DAG: LSHR 98 ; EG-DAG: LSHR 99 ; EG-DAG: LSHR 109 ; EG-DAG: LSHR 119 ; EG-DAG: LSHR 120 ; EG-DAG: LSHR 139 ; EG-DAG: LSHR [all …]`
D	set-dx10.ll	`8 ; CHECK: LSHR 22 ; CHECK: LSHR 34 ; CHECK: LSHR 48 ; CHECK: LSHR 60 ; CHECK: LSHR 74 ; CHECK: LSHR 86 ; CHECK: LSHR 100 ; CHECK: LSHR 112 ; CHECK: LSHR 126 ; CHECK: LSHR [all …]`
D	unsupported-cc.ll	`6 ; CHECK: LSHR 18 ; CHECK: LSHR 33 ; CHECK-NEXT: LSHR * 43 ; CHECK: LSHR 55 ; CHECK: LSHR 67 ; CHECK: LSHR 79 ; CHECK: LSHR 94 ; CHECK-NEXT: LSHR * 104 ; CHECK: LSHR 116 ; CHECK: LSHR`
D	image-resource-id.ll	`8 ; EG-NEXT: LSHR 22 ; EG-NEXT: LSHR 38 ; EG-NEXT: LSHR 52 ; EG-NEXT: LSHR 68 ; EG-NEXT: LSHR 83 ; EG-NEXT: LSHR 98 ; EG-NEXT: LSHR 113 ; EG-NEXT: LSHR 130 ; EG-NEXT: LSHR 145 ; EG-NEXT: LSHR [all …]`
D	load-global-i16.ll	`81 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 107 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 176 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 192 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 282 ; EG-NEXT: LSHR T8.X, T0.W, literal.x, 288 ; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, 322 ; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x, 324 ; CM-NEXT: LSHR * T8.X, T0.W, literal.x, 393 ; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, 409 ; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x, [all …]`
D	r600.extract-lowbits.ll	`27 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 38 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 65 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, 84 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, 102 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 113 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 135 ; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 146 ; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x, 173 ; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x, 192 ; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x, [all …]`
/external/apache-commons-bcel/src/main/java/org/apache/bcel/generic/
D	LSHR.java	`26 public class LSHR extends ArithmeticInstruction { class 28 public LSHR() { in LSHR() method in LSHR 29 super(org.apache.bcel.Const.LSHR); in LSHR()`

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