| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIAddIMGInit.cpp | 80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction() local
83 if (!TFE && !LWE) // intersect_ray in runOnMachineFunction()
87 unsigned LWEVal = LWE->getImm(); in runOnMachineFunction()
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| D | MIMGInstructions.td | 245 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
257 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
270 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
338 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
350 … GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
364 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe),
427 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
455 GLC:$glc, SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe);
471 SLC:$slc, R128A16:$r128, GFX10A16:$a16, TFE:$tfe, LWE:$lwe));
529 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
[all …]
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| D | AMDGPUInstructionSelector.cpp | 1443 static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE, in parseTexFail() argument
1450 LWE = (TexFailCtrl & 0x2) ? 1 : 0; in parseTexFail()
1504 bool LWE; in selectImageIntrinsic() local
1507 TFE, LWE, IsTexFail)) in selectImageIntrinsic()
1710 MIB.addImm(LWE); // lwe in selectImageIntrinsic()
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| D | SIInstrInfo.td | 1117 def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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| D | SIInstrInfo.cpp | 3859 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe); in verifyInstruction() local
3867 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm())) in verifyInstruction()
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| D | SIISelLowering.cpp | 5933 SDValue *LWE, bool &IsTexFail) { in parseTexFail() argument
5944 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32); in parseTexFail()
6192 SDValue LWE; in lowerImage() local
6195 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail)) in lowerImage()
6274 Ops.push_back(LWE); in lowerImage()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIAddIMGInit.cpp | 80 MachineOperand *LWE = TII->getNamedOperand(MI, AMDGPU::OpName::lwe); in runOnMachineFunction() local
85 assert( (TFE && LWE) && "Expected tfe and lwe operands in instruction"); in runOnMachineFunction()
88 unsigned LWEVal = LWE->getImm(); in runOnMachineFunction()
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| D | MIMGInstructions.td | 229 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
241 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
254 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
322 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
334 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
348 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe),
411 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da);
439 GLC:$glc, SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe);
455 SLC:$slc, R128A16:$r128, TFE:$tfe, LWE:$lwe));
513 R128A16:$r128, TFE:$tfe, LWE:$lwe, DA:$da),
[all …]
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| D | SIInstrInfo.td | 1071 def LWE : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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| D | SIInstrInfo.cpp | 3409 const MachineOperand *LWE = getNamedOperand(MI, AMDGPU::OpName::lwe); in verifyInstruction() local
3417 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm())) in verifyInstruction()
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| D | SIISelLowering.cpp | 5317 SDValue *LWE, bool &IsTexFail) { in parseTexFail() argument
5328 *LWE = DAG.getTargetConstant((Value & 0x2) ? 1 : 0, DL, MVT::i32); in parseTexFail()
5529 SDValue LWE; in lowerImage() local
5532 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail)) in lowerImage()
5609 Ops.push_back(LWE); // lwe in lowerImage()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsEVAInstrInfo.td | 181 def LWE : LWE_ENC, LWE_DESC, INSN_EVA;
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsEVAInstrInfo.td | 191 def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
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| D | MipsScheduleP5600.td | 136 LDC2, LDC3, LBE, LBuE, LHE, LHuE, LWE, LLE,
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| D | MipsScheduleGeneric.td | 606 def : InstRW<[GenericWriteLoad], (instrs LBE, LBuE, LHE, LHuE, LWE,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsEVAInstrInfo.td | 191 def LWE : MMRel, LWE_ENC, LWE_DESC, ISA_MIPS32R2, ASE_EVA;
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| D | MipsScheduleP5600.td | 135 LDC2, LDC3, LBE, LBuE, LHE, LHuE, LWE, LLE,
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| D | MipsScheduleGeneric.td | 606 def : InstRW<[GenericWriteLoad], (instrs LBE, LBuE, LHE, LHuE, LWE,
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| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | micromips-eva.mir | 119 …%14:gpr32 = LWE %13, 20 :: (dereferenceable load 4 from `i32* getelementptr inbounds ([13 x i32], …
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.td | 559 def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 700 {DBGFIELD("LWE") 1, false, false, 8, 2, 2, 1, 0, 0}, // #440
2384 {DBGFIELD("LWE") 1, false, false, 40, 2, 4, 1, 0, 0}, // #440
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| D | MipsGenMCCodeEmitter.inc | 1822 UINT64_C(2080374831), // LWE
2947 case Mips::LWE:
11284 CEFBS_HasStdEnc_HasMips32r2_HasEVA_NotInMicroMips, // LWE = 1809
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| D | MipsGenAsmWriter.inc | 3050 25186552U, // LWE
5804 0U, // LWE
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| D | MipsGenInstrInfo.inc | 1824 LWE = 1809,
3220 LWE = 440,
6670 …UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #1809 = LWE
16824 { Mips::LWE, Mips::LWE, Mips::LWE_MM },
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| /external/llvm-project/llvm/test/Transforms/InstCombine/AMDGPU/ |
| D | amdgcn-demanded-vector-elts.ll | 2650 ; Check that the intrinsic remains unchanged in the presence of TFE or LWE
2661 ; Check that the intrinsic remains unchanged in the presence of TFE or LWE
3800 ; TFE / LWE
|