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Searched refs:Ld1 (Results 1 – 14 of 14) sorted by relevance

/external/llvm-project/llvm/test/Analysis/CostModel/SystemZ/
Dload-and-test.ll6 %Ld1 = load i64, i64* %Src
7 %Cmp = icmp eq i64 %Ld1, 0
8 %S = select i1 %Cmp, i64 %Arg, i64 %Ld1
11 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Ld1 = load i64, i64* %Src
12 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Cmp = icmp eq i64 %Ld1, 0
17 %Ld1 = load i32, i32* %Src
18 %Cmp = icmp eq i32 %Ld1, 0
19 %S = select i1 %Cmp, i32 %Arg, i32 %Ld1
22 ; CHECK: Cost Model: Found an estimated cost of 1 for instruction: %Ld1 = load i32, i32* %Src
23 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Cmp = icmp eq i32 %Ld1, 0
Dintrinsics.ll49 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Ld1 = load i64, i64* %src
50 …el: Found an estimated cost of 1 for instruction: %swp1 = tail call i64 @llvm.bswap.i64(i64 %Ld1)
56 %Ld1 = load i64, i64* %src
57 %swp1 = tail call i64 @llvm.bswap.i64(i64 %Ld1)
71 ; Z13: Cost Model: Found an estimated cost of 1 for instruction: %Ld1 = load <2 x i64>, <2 x i6…
72 ; Z15: Cost Model: Found an estimated cost of 0 for instruction: %Ld1 = load <2 x i64>, <2 x i6…
73 …stimated cost of 1 for instruction: %swp1 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld1)
82 %Ld1 = load <2 x i64>, <2 x i64>* %src
83 %swp1 = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %Ld1)
97 ; CHECK: Cost Model: Found an estimated cost of 0 for instruction: %Ld1 = load i32, i32* %src
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMParallelDSP.cpp229 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
311 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
313 if (!Ld0 || !Ld1) in AreSequentialLoads()
316 if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1) in AreSequentialLoads()
321 dbgs() << "Ld1:"; Ld1->dump(); in AreSequentialLoads()
326 VecMem.push_back(Ld1); in AreSequentialLoads()
571 auto Ld1 = static_cast<LoadInst*>(PMul1->LHS); in CreateParallelPairs() local
576 if (Ld0 == Ld2 || Ld1 == Ld3) in CreateParallelPairs()
579 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) { in CreateParallelPairs()
590 } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) && in CreateParallelPairs()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMParallelDSP.cpp228 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
310 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
312 if (!Ld0 || !Ld1) in AreSequentialLoads()
315 if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1) in AreSequentialLoads()
320 dbgs() << "Ld1:"; Ld1->dump(); in AreSequentialLoads()
325 VecMem.push_back(Ld1); in AreSequentialLoads()
570 auto Ld1 = static_cast<LoadInst*>(PMul1->LHS); in CreateParallelPairs() local
574 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) { in CreateParallelPairs()
585 } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) && in CreateParallelPairs()
/external/vixl/examples/aarch64/
Dadd2-vectors.cc59 __ Ld1(v0.V16B(), MemOperand(x0)); in GenerateAdd2Vectors() local
60 __ Ld1(v1.V16B(), MemOperand(x1, 16, PostIndex)); in GenerateAdd2Vectors() local
Dneon-matrix-multiply.cc73 __ Ld1(v4.V4S(), v5.V4S(), v6.V4S(), v7.V4S(), MemOperand(x1)); in GenerateNEONMatrixMultiply() local
75 __ Ld1(v16.V4S(), v17.V4S(), v18.V4S(), v19.V4S(), MemOperand(x2)); in GenerateNEONMatrixMultiply() local
/external/vixl/test/aarch64/
Dtest-disasm-neon-aarch64.cc349 COMPARE_MACRO(Ld1(v0.M, MemOperand(x15)), "ld1 {v0." S "}, [x15]"); \ in TEST()
350 COMPARE_MACRO(Ld1(v1.M, v2.M, MemOperand(x16)), \ in TEST()
352 COMPARE_MACRO(Ld1(v3.M, v4.M, v5.M, MemOperand(x17)), \ in TEST()
354 COMPARE_MACRO(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18)), \ in TEST()
356 COMPARE_MACRO(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp)), \ in TEST()
370 COMPARE_MACRO(Ld1(v0.M, MemOperand(x15, x20, PostIndex)), \ in TEST()
372 COMPARE_MACRO(Ld1(v1.M, v2.M, MemOperand(x16, x21, PostIndex)), \ in TEST()
374 COMPARE_MACRO(Ld1(v3.M, v4.M, v5.M, MemOperand(x17, x22, PostIndex)), \ in TEST()
376 COMPARE_MACRO(Ld1(v6.M, v7.M, v8.M, v9.M, MemOperand(x18, x23, PostIndex)), \ in TEST()
378 COMPARE_MACRO(Ld1(v30.M, v31.M, v0.M, v1.M, MemOperand(sp, x24, PostIndex)), \ in TEST()
[all …]
Dtest-assembler-neon-aarch64.cc312 __ Ld1(v2.V8B(), MemOperand(x17)); in TEST() local
314 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x17)); in TEST() local
316 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x17)); in TEST() local
318 __ Ld1(v16.V2S(), v17.V2S(), v18.V2S(), v19.V2S(), MemOperand(x17)); in TEST() local
320 __ Ld1(v30.V2S(), v31.V2S(), v0.V2S(), v1.V2S(), MemOperand(x17)); in TEST() local
322 __ Ld1(v20.V1D(), v21.V1D(), v22.V1D(), v23.V1D(), MemOperand(x17)); in TEST() local
368 __ Ld1(v2.V8B(), MemOperand(x17, x23, PostIndex)); in TEST() local
369 __ Ld1(v3.V8B(), v4.V8B(), MemOperand(x18, 16, PostIndex)); in TEST() local
370 __ Ld1(v5.V4H(), v6.V4H(), v7.V4H(), MemOperand(x19, 24, PostIndex)); in TEST() local
371 __ Ld1(v16.V2S(), in TEST() local
[all …]
Dtest-assembler-aarch64.cc11925 __ Ld1(v0.V16B(), MemOperand(x10, x11, PostIndex)); in TEST() local
/external/llvm-project/llvm/test/Transforms/LoopVectorize/AArch64/
Dreduction-small-size.ll127 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8>
128 ; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16>
/external/llvm/test/Transforms/LoopVectorize/AArch64/
Dreduction-small-size.ll141 ; CHECK: [[Ld1:%[a-zA-Z0-9.]+]] = load <8 x i8>
142 ; CHECK: zext <8 x i8> [[Ld1]] to <8 x i16>
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dshuff-combos-128b.ll201 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vshuff(v[[Hd0]],v[[Ld0]],[[Rd1]])
202 ; CHECK: v[[Hd2:[0-9]+]]:[[Ld2:[0-9]+]] = vdeal(v[[Hd1]],v[[Ld1]],[[Rd2]])
Dshuff-combos-64b.ll187 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vdeal(v[[Hd0]],v[[Ld0]],[[Rd1]])
/external/vixl/src/aarch64/
Dmacro-assembler-aarch64.h3173 void Ld1(const VRegister& vt, const MemOperand& src) { in Ld1() function
3178 void Ld1(const VRegister& vt, const VRegister& vt2, const MemOperand& src) { in Ld1() function
3183 void Ld1(const VRegister& vt, in Ld1() function
3191 void Ld1(const VRegister& vt, in Ld1() function
3200 void Ld1(const VRegister& vt, int lane, const MemOperand& src) { in Ld1() function