/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument 802 switch (LdSt.getOpcode()) { in getMemOperandWithOffset() 815 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset()
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D | LanaiInstrInfo.h | 70 bool getMemOperandWithOffset(const MachineInstr &LdSt, 75 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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/external/llvm-project/llvm/lib/Target/Lanai/ |
D | LanaiSchedule.td | 55 def LdSt : ProcResource<1> { let BufferSize = 0; } 64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 762 if (LdSt.getNumOperands() != 4) in getMemOperandWithOffsetWidth() 764 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOperandWithOffsetWidth() 765 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOperandWithOffsetWidth() 768 switch (LdSt.getOpcode()) { in getMemOperandWithOffsetWidth() 789 BaseOp = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 790 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth() 799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 802 switch (LdSt.getOpcode()) { in getMemOperandsWithOffsetWidth() 816 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth()
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D | LanaiInstrInfo.h | 71 const MachineInstr &LdSt, 76 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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/external/llvm/lib/Target/Lanai/ |
D | LanaiSchedule.td | 56 def LdSt : ProcResource<1> { let BufferSize = 0; } 65 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; } 66 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; } 67 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; } 68 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
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D | LanaiInstrInfo.cpp | 751 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth() argument 755 if (LdSt.getNumOperands() != 4) in getMemOpBaseRegImmOfsWidth() 757 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm() || in getMemOpBaseRegImmOfsWidth() 758 !(LdSt.getOperand(3).isImm() && LdSt.getOperand(3).getImm() == LPAC::ADD)) in getMemOpBaseRegImmOfsWidth() 761 switch (LdSt.getOpcode()) { in getMemOpBaseRegImmOfsWidth() 782 BaseReg = LdSt.getOperand(1).getReg(); in getMemOpBaseRegImmOfsWidth() 783 Offset = LdSt.getOperand(2).getImm(); in getMemOpBaseRegImmOfsWidth() 788 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs() argument 790 switch (LdSt.getOpcode()) { in getMemOpBaseRegImmOfs() 803 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs()
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D | LanaiInstrInfo.h | 70 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, 74 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.cpp | 563 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 565 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth() 571 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth() 573 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth() 576 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth() 579 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth() 580 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 581 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
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D | RISCVInstrInfo.h | 89 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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/external/llvm-project/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.cpp | 631 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 633 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffsetWidth() 639 if (LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth() 641 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth() 644 if (!LdSt.hasOneMemOperand()) in getMemOperandWithOffsetWidth() 647 Width = (*LdSt.memoperands_begin())->getSize(); in getMemOperandWithOffsetWidth() 648 BaseReg = &LdSt.getOperand(1); in getMemOperandWithOffsetWidth() 649 Offset = LdSt.getOperand(2).getImm(); in getMemOperandWithOffsetWidth()
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D | RISCVInstrInfo.h | 92 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs() argument 208 unsigned Opc = LdSt.getOpcode(); in getMemOpBaseRegImmOfs() 210 if (isDS(LdSt)) { in getMemOpBaseRegImmOfs() 212 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOpBaseRegImmOfs() 216 getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOpBaseRegImmOfs() 227 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOpBaseRegImmOfs() 229 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOpBaseRegImmOfs() 239 if (LdSt.mayLoad()) in getMemOpBaseRegImmOfs() 240 EltSize = getOpRegClass(LdSt, 0)->getSize() / 2; in getMemOpBaseRegImmOfs() 242 assert(LdSt.mayStore()); in getMemOpBaseRegImmOfs() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.h | 96 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, 100 bool getMemOpBaseRegImmOfsWidth(MachineInstr &LdSt, unsigned &BaseReg,
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D | AArch64InstrInfo.cpp | 1538 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs() argument 1540 switch (LdSt.getOpcode()) { in getMemOpBaseRegImmOfs() 1568 return getMemOpBaseRegImmOfsWidth(LdSt, BaseReg, Offset, Width, TRI); in getMemOpBaseRegImmOfs() 1573 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth() argument 1575 assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); in getMemOpBaseRegImmOfsWidth() 1577 if (LdSt.getNumExplicitOperands() == 3) { in getMemOpBaseRegImmOfsWidth() 1579 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isImm()) in getMemOpBaseRegImmOfsWidth() 1581 } else if (LdSt.getNumExplicitOperands() == 4) { in getMemOpBaseRegImmOfsWidth() 1583 if (!LdSt.getOperand(1).isReg() || !LdSt.getOperand(2).isReg() || in getMemOpBaseRegImmOfsWidth() 1584 !LdSt.getOperand(3).isImm()) in getMemOpBaseRegImmOfsWidth() [all …]
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 273 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 276 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth() 279 unsigned Opc = LdSt.getOpcode(); in getMemOperandsWithOffsetWidth() 284 if (isDS(LdSt)) { in getMemOperandsWithOffsetWidth() 285 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth() 286 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth() 300 Width = getOpSize(LdSt, DataOpIdx); in getMemOperandsWithOffsetWidth() 306 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth() 308 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandsWithOffsetWidth() 319 if (LdSt.mayLoad()) in getMemOperandsWithOffsetWidth() [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SIInstrInfo.cpp | 261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument 265 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffset() 268 unsigned Opc = LdSt.getOpcode(); in getMemOperandWithOffset() 270 if (isDS(LdSt)) { in getMemOperandWithOffset() 272 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandWithOffset() 275 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandWithOffset() 290 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandWithOffset() 292 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandWithOffset() 302 if (LdSt.mayLoad()) in getMemOperandWithOffset() 303 EltSize = TRI->getRegSizeInBits(*getOpRegClass(LdSt, 0)) / 16; in getMemOperandWithOffset() [all …]
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/external/llvm-project/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 2294 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 2299 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI)) in getMemOperandsWithOffsetWidth() 2305 static bool isLdStSafeToCluster(const MachineInstr &LdSt, in isLdStSafeToCluster() argument 2308 if (LdSt.hasOrderedMemoryRef() || LdSt.getNumExplicitOperands() != 3) in isLdStSafeToCluster() 2311 if (LdSt.getOperand(2).isFI()) in isLdStSafeToCluster() 2314 assert(LdSt.getOperand(2).isReg() && "Expected a reg operand."); in isLdStSafeToCluster() 2317 if (LdSt.modifiesRegister(LdSt.getOperand(2).getReg(), TRI)) in isLdStSafeToCluster() 5043 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 5045 if (!LdSt.mayLoadOrStore() || LdSt.getNumExplicitOperands() != 3) in getMemOperandWithOffsetWidth() 5049 if (!LdSt.getOperand(1).isImm() || in getMemOperandWithOffsetWidth() [all …]
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D | PPCInstrInfo.h | 512 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 520 const MachineInstr &LdSt,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 1981 bool AArch64InstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset() argument 1985 if (!LdSt.mayLoadOrStore()) in getMemOperandWithOffset() 1989 return getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, Width, TRI); in getMemOperandWithOffset() 1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 1995 assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); in getMemOperandWithOffsetWidth() 1997 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth() 1999 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth() 2000 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth() 2002 } else if (LdSt.getNumExplicitOperands() == 4) { in getMemOperandWithOffsetWidth() 2004 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth() [all …]
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D | AArch64InstrInfo.h | 126 MachineOperand &getMemOpBaseRegImmOfsOffsetOperand(MachineInstr &LdSt) const;
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 2133 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth() argument 2136 if (!LdSt.mayLoadOrStore()) in getMemOperandsWithOffsetWidth() 2140 if (!getMemOperandWithOffsetWidth(LdSt, BaseOp, Offset, OffsetIsScalable, in getMemOperandsWithOffsetWidth() 2166 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth() argument 2169 assert(LdSt.mayLoadOrStore() && "Expected a memory operation."); in getMemOperandWithOffsetWidth() 2171 if (LdSt.getNumExplicitOperands() == 3) { in getMemOperandWithOffsetWidth() 2173 if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) || in getMemOperandWithOffsetWidth() 2174 !LdSt.getOperand(2).isImm()) in getMemOperandWithOffsetWidth() 2176 } else if (LdSt.getNumExplicitOperands() == 4) { in getMemOperandWithOffsetWidth() 2178 if (!LdSt.getOperand(1).isReg() || in getMemOperandWithOffsetWidth() [all …]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfo.h | 192 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.h | 362 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt,
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