| /external/llvm-project/clang-tools-extra/clang-tidy/misc/ |
| D | RedundantExpressionCheck.cpp | 785 SourceRange Lsr = LhsExpr->getSourceRange(); in areExprsFromDifferentMacros() local
787 if (!Lsr.getBegin().isMacroID() || !Rsr.getBegin().isMacroID()) in areExprsFromDifferentMacros()
794 SM.getDecomposedLoc(SM.getExpansionLoc(Lsr.getBegin())); in areExprsFromDifferentMacros()
812 !isTokAtEndOfExpr(Lsr, LTok, SM) && in areExprsFromDifferentMacros()
814 return (!isTokAtEndOfExpr(Lsr, LTok, SM) || in areExprsFromDifferentMacros()
|
| /external/vixl/test/aarch32/ |
| D | test-disasm-a32.cc | 3461 COMPARE_T32(Lsr(eq, r0, r1, 16), in TEST()
3465 COMPARE_T32(Lsr(eq, r0, r1, 32), in TEST()
3469 COMPARE_T32(Lsr(eq, r0, r1, 0), in TEST()
3475 COMPARE_T32(Lsr(eq, r7, r7, r3), in TEST()
3479 COMPARE_T32(Lsr(eq, r8, r8, r3), in TEST()
4061 CHECK_T32_16(Lsr(DontCare, r0, r1, 32), "lsrs r0, r1, #32\n"); in TEST()
4063 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r1, 32), in TEST()
4067 CHECK_T32_16(Lsr(DontCare, r0, r0, r1), "lsrs r0, r1\n"); in TEST()
4069 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r0, r1), in TEST()
|
| D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 146 M(Lsr) \
|
| D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 146 M(Lsr) \
|
| D | test-assembler-aarch32.cc | 784 __ Lsr(r4, r1, 8); in TEST() local
810 __ Lsr(r4, r1, r9); in TEST() local
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineInternal.h | 528 Value *SimplifyShrShlDemandedBits(Instruction *Lsr, Instruction *Sftl,
|
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| D | assembler_arm.h | 998 void Lsr(Register rd, Register rm, const Operand& shift_imm,
1001 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
|
| D | assembler_arm.cc | 2458 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2470 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
|
| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 8592 __ Lsr(x1, x1, 1); in TEST_SVE() local
8601 __ Lsr(x2, x2, 2); in TEST_SVE() local
9586 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000 in TEST_SVE() local
9591 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000 in TEST_SVE() local
9596 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000 in TEST_SVE() local
9780 __ Lsr(z29.VnD(), z28.VnD(), 1); // Shift right to 0x4000000040000000 in TEST_SVE() local
9785 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x2000000020000000 in TEST_SVE() local
9790 __ Lsr(z29.VnD(), z29.VnD(), 1); // Shift right to 0x1000000010000000 in TEST_SVE() local
9957 __ Lsr(zn, zn, shift); in GatherLoadScalarPlusVectorHelper() local
10482 __ Lsr(x1, x1, 1); in TEST_SVE() local
[all …]
|
| D | test-assembler-aarch64.cc | 6222 __ Lsr(x16, x0, x1); in TEST() local
6223 __ Lsr(x17, x0, x2); in TEST() local
6224 __ Lsr(x18, x0, x3); in TEST() local
6225 __ Lsr(x19, x0, x4); in TEST() local
6226 __ Lsr(x20, x0, x5); in TEST() local
6227 __ Lsr(x21, x0, x6); in TEST() local
6229 __ Lsr(w22, w0, w1); in TEST() local
6230 __ Lsr(w23, w0, w2); in TEST() local
6231 __ Lsr(w24, w0, w3); in TEST() local
6232 __ Lsr(w25, w0, w4); in TEST() local
[all …]
|
| D | test-disasm-sve-aarch64.cc | 308 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z4.VnB(), z30.VnB()), in TEST()
310 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z30.VnB(), z4.VnB()), in TEST()
312 COMPARE_MACRO(Lsr(z4.VnB(), p0.Merging(), z10.VnB(), z14.VnB()), in TEST()
358 COMPARE_MACRO(Lsr(z24.VnD(), p2.Merging(), z0.VnD(), 64), in TEST()
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 399 Lsr, enumerator
1010 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
|
| D | IceInstARM32.cpp | 3493 template class InstARM32ThreeAddrGPR<InstARM32::Lsr>;
|
| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 2035 void Lsr(const Register& rd, const Register& rn, unsigned shift) { in Lsr() function
2042 void Lsr(const Register& rd, const Register& rn, const Register& rm) { in Lsr() function
5232 void Lsr(const ZRegister& zd, in Lsr() function
5240 void Lsr(const ZRegister& zd,
5244 void Lsr(const ZRegister& zd, const ZRegister& zn, int shift) { in Lsr() function
5249 void Lsr(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm) { in Lsr() function
|
| D | macro-assembler-sve-aarch64.cc | 595 void MacroAssembler::Lsr(const ZRegister& zd, in Lsr() function in vixl::aarch64::MacroAssembler
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 2321 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { in Lsr() function
2338 void Lsr(Register rd, Register rm, const Operand& operand) { in Lsr() function
2339 Lsr(al, rd, rm, operand); in Lsr()
2341 void Lsr(FlagsUpdate flags, in Lsr() function
2348 Lsr(cond, rd, rm, operand); in Lsr()
2362 Lsr(cond, rd, rm, operand); in Lsr()
2367 void Lsr(FlagsUpdate flags, in Lsr() function
2371 Lsr(flags, al, rd, rm, operand); in Lsr()
|