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Searched refs:M64 (Results 1 – 19 of 19) sorted by relevance

/external/llvm/test/CodeGen/X86/
Dwin64_alloca_dynalloca.ll1 …%s -mcpu=generic -enable-misched=false -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64
9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
20 ; M64: leaq 128(%rsp), %rbp
40 ; M64: leaq 15(%{{.*}}), %rax
41 ; M64: andq $-16, %rax
42 ; M64: callq ___chkstk_ms
43 ; M64: subq %rax, %rsp
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dwin64_alloca_dynalloca.ll1 …%s -mcpu=generic -enable-misched=false -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64
9 ; M64-LABEL: unaligned:
17 ; M64: $4096, %eax
18 ; M64: callq ___chkstk_ms
19 ; M64: subq %rax, %rsp
20 ; M64: leaq 128(%rsp), %rbp
40 ; M64: leaq 15(%{{.*}}), %rax
41 ; M64: andq $-16, %rax
42 ; M64: callq ___chkstk_ms
43 ; M64: subq %rax, %rsp
[all …]
/external/mesa3d/src/panfrost/midgard/
Dmidgard_ops.c181 #define M64 midgard_reg_mode_64 macro
203 …[midgard_op_atomic_add64] = {"atomic_add64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
204 …[midgard_op_atomic_and64] = {"atomic_and64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
205 …[midgard_op_atomic_or64] = {"atomic_or64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
206 …[midgard_op_atomic_xor64] = {"atomic_xor64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
207 …[midgard_op_atomic_imin64] = {"atomic_imin64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
208 …[midgard_op_atomic_umin64] = {"atomic_umin64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
209 …[midgard_op_atomic_imax64] = {"atomic_imax64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
210 …[midgard_op_atomic_umax64] = {"atomic_umax64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
211 …[midgard_op_atomic_xchg64] = {"atomic_xchg64", M64 | LDST_SIDE_FX | LDST_ADDRESS | LDST_ATOM…
[all …]
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dstore-atomic.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,M64
6 ; RUN: FileCheck %s -check-prefixes=ALL,M64
36 ; M64-LABEL: store_i64
38 ; M64: sync
39 ; M64: sd $5, 0($4)
Dload-atomic.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,M64
6 ; RUN: FileCheck %s -check-prefixes=ALL,M64
36 ; M64-LABEL: load_i64
38 ; M64: ld $2, 0($4)
39 ; M64: sync
Dfptosi.ll17 ; RUN: FileCheck %s -check-prefixes=M64
19 ; RUN: FileCheck %s -check-prefixes=M64
21 ; RUN: FileCheck %s -check-prefixes=M64
115 ; M64-LABEL: test1:
116 ; M64: # %bb.0: # %entry
117 ; M64-NEXT: trunc.w.s $f0, $f12 # <MCInst #{{[0-9]+}} TRUNC_W_S
118 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
119 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
120 ; M64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
121 ; M64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
[all …]
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dstore-atomic.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,M64
6 ; RUN: FileCheck %s -check-prefixes=ALL,M64
36 ; M64-LABEL: store_i64
38 ; M64: sync
39 ; M64: sd $5, 0($4)
Dload-atomic.ll4 ; RUN: FileCheck %s -check-prefixes=ALL,M64
6 ; RUN: FileCheck %s -check-prefixes=ALL,M64
36 ; M64-LABEL: load_i64
38 ; M64: ld $2, 0($4)
39 ; M64: sync
/external/bouncycastle/repackaged/bcprov/src/main/java/com/android/org/bouncycastle/math/raw/
DInterleave.java10 private static final long M64 = 0x5555555555555555L; field in Interleave
94 z[zOff ] = (x ) & M64; in expand64To128()
95 z[zOff + 1] = (x >>> 1) & M64; in expand64To128()
/external/bouncycastle/repackaged_platform/bcprov/src/main/java/com/android/internal/org/bouncycastle/math/raw/
DInterleave.java10 private static final long M64 = 0x5555555555555555L; field in Interleave
94 z[zOff ] = (x ) & M64; in expand64To128()
95 z[zOff + 1] = (x >>> 1) & M64; in expand64To128()
/external/bouncycastle/bcprov/src/main/java/org/bouncycastle/math/raw/
DInterleave.java6 private static final long M64 = 0x5555555555555555L; field in Interleave
90 z[zOff ] = (x ) & M64; in expand64To128()
91 z[zOff + 1] = (x >>> 1) & M64; in expand64To128()
/external/llvm-project/llvm/test/Transforms/LoopVectorize/
Dexplicit_outer_uniform_diverg_branch.ll37 %M64 = zext i32 %M to i64
61 %exitcond = icmp eq i64 %indvars.iv.next, %M64
89 %M64 = zext i32 %M to i64
113 %exitcond = icmp eq i64 %indvars.iv.next, %M64
/external/llvm-project/clang/test/CodeGenOpenCL/
Dshifts.cl36 //OPT: [[M64:%.+]] = and i64 %b, 63
37 //OPT-NEXT: [[C64:%.+]] = ashr i64 %a, [[M64]]
/external/clang/test/CodeGenOpenCL/
Dshifts.cl36 //OPT: [[M64:%.+]] = and i64 %b, 63
37 //OPT-NEXT: [[C64:%.+]] = ashr i64 %a, [[M64]]
/external/llvm-project/polly/test/ScopInfo/
Duser_provided_assumptions.ll72 %M64 = sext i32 %M to i64
83 %cmp20 = icmp eq i64 %indvars.iv, %M64
87 %tmp9 = mul nsw i64 %indvars.iv3, %M64
Dremarks.ll67 %M64 = sext i32 %M to i64, !dbg !45
81 %cmp4 = icmp eq i64 %indvars.iv, %M64, !dbg !55
85 %tmp8 = mul i64 %indvars.iv3, %M64, !dbg !59
/external/rust/crates/nom/tests/
Dmp4.rs174 MvhdBox::M64(Mvhd64 {
203 M64(Mvhd64), enumerator
/external/llvm-project/clang/lib/Driver/ToolChains/
DGnu.cpp1063 Multilib M64 = Multilib() in findMipsCsMultilibs() local
1073 MultilibSet().Either(M32, M64, MAbiN32).FilterOut(NonExistent); in findMipsCsMultilibs()
/external/clang/lib/Driver/
DToolChains.cpp1985 Multilib M64 = Multilib() in findMipsCsMultilibs() local
1995 MultilibSet().Either(M32, M64, MAbiN32).FilterOut(NonExistent); in findMipsCsMultilibs()