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Searched refs:MAX_RTS (Results 1 – 12 of 12) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_constants.h35 #define MAX_RTS 8 macro
Dradv_meta_clear.c297 VkPipelineColorBlendAttachmentState blend_attachment_state[MAX_RTS] = { 0 }; in create_color_pipeline()
309 .attachmentCount = MAX_RTS, in create_color_pipeline()
Dradv_private.h1394 uint8_t cb_mip[MAX_RTS];
Dradv_device.c1616 .maxColorAttachments = MAX_RTS, in radv_GetPhysicalDeviceProperties()
/external/mesa3d/src/intel/vulkan/
Danv_pipeline.c523 assert(subpass->color_count <= MAX_RTS); in populate_wm_prog_key()
983 struct anv_pipeline_binding rt_bindings[MAX_RTS]; in anv_pipeline_link_fs()
985 assert(stage->key.wm.nr_color_regions <= MAX_RTS); in anv_pipeline_link_fs()
1010 assert(num_rt_bindings <= MAX_RTS); in anv_pipeline_link_fs()
1041 assert(rt + array_len <= MAX_RTS); in anv_pipeline_link_fs()
1043 if (rt >= MAX_RTS || !(stage->key.wm.color_outputs_valid & in anv_pipeline_link_fs()
Danv_descriptor_set.c335 if (surface_count[s] > MAX_BINDING_TABLE_SIZE - MAX_RTS) in anv_GetDescriptorSetLayoutSupport()
Danv_device.c1510 ? UINT32_MAX : MAX_BINDING_TABLE_SIZE - MAX_RTS - 1; in anv_GetPhysicalDeviceProperties()
1611 .maxColorAttachments = MAX_RTS, in anv_GetPhysicalDeviceProperties()
Danv_private.h170 #define MAX_RTS 8 macro
/external/mesa3d/src/freedreno/vulkan/
Dtu_private.h90 #define MAX_RTS 8 macro
314 GLOBAL_SH_FS_CLEAR_MAX = GLOBAL_SH_FS_CLEAR0 + MAX_RTS,
Dtu_device.c659 .maxPerStageDescriptorInputAttachments = MAX_RTS, in tu_GetPhysicalDeviceProperties2()
668 .maxDescriptorSetInputAttachments = MAX_RTS, in tu_GetPhysicalDeviceProperties2()
724 .maxColorAttachments = MAX_RTS, in tu_GetPhysicalDeviceProperties2()
Dtu_pipeline.c264 VkFormat color_attachment_formats[MAX_RTS];
1865 const VkFormat attachment_formats[MAX_RTS], in tu6_emit_rb_mrt_controls() argument
Dtu_clear_blit.c340 for (uint32_t num_rts = 0; num_rts <= MAX_RTS; num_rts++) { in tu_init_clear_blit_shaders()
1809 uint32_t clear_value[MAX_RTS][4]; in tu_clear_sysmem_attachments()