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Searched refs:MAY_HAVE_SSE4_1 (Results 1 – 3 of 3) sorted by relevance

/external/libopus/silk/x86/
Dx86_silk_map.c52 MAY_HAVE_SSE4_1( silk_inner_prod16_aligned_64 ), /* sse4.1 */
53 MAY_HAVE_SSE4_1( silk_inner_prod16_aligned_64 ) /* avx */
65 MAY_HAVE_SSE4_1( silk_VAD_GetSA_Q8 ), /* sse4.1 */
66 MAY_HAVE_SSE4_1( silk_VAD_GetSA_Q8 ) /* avx */
90 MAY_HAVE_SSE4_1( silk_NSQ ), /* sse4.1 */
91 MAY_HAVE_SSE4_1( silk_NSQ ) /* avx */
112 MAY_HAVE_SSE4_1( silk_VQ_WMat_EC ), /* sse4.1 */
113 MAY_HAVE_SSE4_1( silk_VQ_WMat_EC ) /* avx */
138 MAY_HAVE_SSE4_1( silk_NSQ_del_dec ), /* sse4.1 */
139 MAY_HAVE_SSE4_1( silk_NSQ_del_dec ) /* avx */
[all …]
/external/libopus/celt/x86/
Dx86_celt_map.c55 MAY_HAVE_SSE4_1(celt_fir), /* sse4.1 */
56 MAY_HAVE_SSE4_1(celt_fir) /* avx */
68 MAY_HAVE_SSE4_1(xcorr_kernel), /* sse4.1 */
69 MAY_HAVE_SSE4_1(xcorr_kernel) /* avx */
85 MAY_HAVE_SSE4_1(celt_inner_prod), /* sse4.1 */
86 MAY_HAVE_SSE4_1(celt_inner_prod) /* avx */
Dx86cpu.h44 # define MAY_HAVE_SSE4_1(name) name ## _sse4_1 macro
46 # define MAY_HAVE_SSE4_1(name) name ## _c macro