| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | store.ll | 20 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
21 ; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
23 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
25 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
26 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
27 ; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
32 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
33 ; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
35 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
37 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
[all …]
|
| D | load.ll | 21 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
22 ; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
24 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
26 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
27 ; MIPS32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
28 ; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
33 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
34 ; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
36 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
38 ; MMR3-NEXT: # <MCOperand Reg:{{[0-9]+}}>
[all …]
|
| D | fptosi.ll | 42 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
43 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
45 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
47 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>
48 ; M32-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
53 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
54 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
56 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
58 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>
59 ; M32R2-FP64-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
[all …]
|
| /external/llvm-project/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
|
| D | conditional_inst.s | 10 ! CHECK-NEXT: <MCOperand Reg:12>>
16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
30 ! CHECK-NEXT: <MCOperand Expr:(jump1)>
31 ! CHECK-NEXT: <MCOperand Imm:13>
37 ! CHECK-NEXT: <MCOperand Expr:(jump2)>
38 ! CHECK-NEXT: <MCOperand Imm:10>
46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
52 ! CHECK-NEXT: <MCOperand Reg:26>
[all …]
|
| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
|
| D | conditional_inst.s | 10 ! CHECK-NEXT: <MCOperand Reg:12>>
16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
30 ! CHECK-NEXT: <MCOperand Expr:(jump1)>
31 ! CHECK-NEXT: <MCOperand Imm:13>
37 ! CHECK-NEXT: <MCOperand Expr:(jump2)>
38 ! CHECK-NEXT: <MCOperand Imm:10>
46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
52 ! CHECK-NEXT: <MCOperand Reg:26>
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 32 class MCOperand; variable
60 MCOperand createRegOperand(unsigned int RegId) const;
61 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
62 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
64 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
73 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
74 MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
76 MCOperand decodeOperand_VS_32(unsigned Val) const;
77 MCOperand decodeOperand_VS_64(unsigned Val) const;
78 MCOperand decodeOperand_VS_128(unsigned Val) const;
[all …]
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 33 class MCOperand; variable
61 MCOperand createRegOperand(unsigned int RegId) const;
62 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
63 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
65 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
101 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
102 MCOperand decodeOperand_VRegOrLds_32(unsigned Val) const;
104 MCOperand decodeOperand_VS_32(unsigned Val) const;
105 MCOperand decodeOperand_VS_64(unsigned Val) const;
106 MCOperand decodeOperand_VS_128(unsigned Val) const;
[all …]
|
| /external/llvm-project/llvm/lib/Target/VE/ |
| D | VEAsmPrinter.cpp | 69 static MCOperand createVEMCOperand(VEMCExpr::VariantKind Kind, MCSymbol *Sym, in createVEMCOperand()
73 return MCOperand::createExpr(expr); in createVEMCOperand()
76 static MCOperand createGOTRelExprOp(VEMCExpr::VariantKind Kind, in createGOTRelExprOp()
80 return MCOperand::createExpr(expr); in createGOTRelExprOp()
83 static void emitSIC(MCStreamer &OutStreamer, MCOperand &RD, in emitSIC()
91 static void emitBSIC(MCStreamer &OutStreamer, MCOperand &R1, MCOperand &R2, in emitBSIC()
97 MCOperand czero = MCOperand::createImm(0); in emitBSIC()
103 static void emitLEAzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, in emitLEAzzi()
108 MCOperand CZero = MCOperand::createImm(0); in emitLEAzzi()
115 static void emitLEASLzzi(MCStreamer &OutStreamer, MCOperand &Imm, MCOperand &RD, in emitLEASLzzi()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 26 class MCOperand; variable
46 MCOperand createRegOperand(unsigned int RegId) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
48 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
50 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
57 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
58 MCOperand decodeOperand_VS_32(unsigned Val) const;
59 MCOperand decodeOperand_VS_64(unsigned Val) const;
61 MCOperand decodeOperand_VReg_64(unsigned Val) const;
62 MCOperand decodeOperand_VReg_96(unsigned Val) const;
[all …]
|
| D | AMDGPUDisassembler.cpp | 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
169 MCOperand AMDGPUDisassembler::errOperand(unsigned V, in errOperand()
175 return MCOperand(); in errOperand()
179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand()
180 return MCOperand::createReg(RegId); in createRegOperand()
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, in createSRegOperand()
229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
[all …]
|
| /external/capstone/ |
| D | MCInst.h | 26 typedef struct MCOperand MCOperand; typedef
30 struct MCOperand { struct
46 bool MCOperand_isValid(const MCOperand *op); argument
48 bool MCOperand_isReg(const MCOperand *op);
50 bool MCOperand_isImm(const MCOperand *op);
52 bool MCOperand_isFPImm(const MCOperand *op);
54 bool MCOperand_isInst(const MCOperand *op);
57 unsigned MCOperand_getReg(const MCOperand *op);
60 void MCOperand_setReg(MCOperand *op, unsigned Reg);
62 int64_t MCOperand_getImm(MCOperand *op);
[all …]
|
| D | MCInst.c | 44 void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) in MCInst_insert0()
76 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) in MCInst_getOperand()
87 void MCInst_addOperand2(MCInst *inst, MCOperand *Op) in MCInst_addOperand2()
94 bool MCOperand_isValid(const MCOperand *op) in MCOperand_isValid()
99 bool MCOperand_isReg(const MCOperand *op) in MCOperand_isReg()
104 bool MCOperand_isImm(const MCOperand *op) in MCOperand_isImm()
109 bool MCOperand_isFPImm(const MCOperand *op) in MCOperand_isFPImm()
115 unsigned MCOperand_getReg(const MCOperand *op) in MCOperand_getReg()
121 void MCOperand_setReg(MCOperand *op, unsigned Reg) in MCOperand_setReg()
126 int64_t MCOperand_getImm(MCOperand *op) in MCOperand_getImm()
[all …]
|
| /external/llvm-project/llvm/test/CodeGen/Mips/ |
| D | micromips-pseudo-mtlohi-expand.ll | 11 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
12 ; MMR2-NEXT: # <MCOperand Imm:0>>
14 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
15 ; MMR2-NEXT: # <MCOperand Imm:1>>
17 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
19 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
21 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>
22 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
24 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
26 ; MMR2-NEXT: # <MCOperand Reg:{{[0-9]+}}>>
[all …]
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
|
| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand createReg(unsigned Reg) { in createReg()
112 MCOperand Op; in createReg()
117 static MCOperand createImm(int64_t Val) { in createImm()
118 MCOperand Op; in createImm()
123 static MCOperand createFPImm(double Val) { in createFPImm()
124 MCOperand Op; in createFPImm()
129 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
130 MCOperand Op; in createExpr()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 622 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
628 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
642 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
656 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
693 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/MC/ |
| D | MCInst.h | 34 class MCOperand {
54 MCOperand() : FPImmVal(0.0) {} in MCOperand() function
115 static MCOperand createReg(unsigned Reg) { in createReg()
116 MCOperand Op; in createReg()
122 static MCOperand createImm(int64_t Val) { in createImm()
123 MCOperand Op; in createImm()
129 static MCOperand createFPImm(double Val) { in createFPImm()
130 MCOperand Op; in createFPImm()
136 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
137 MCOperand Op; in createExpr()
[all …]
|
| /external/llvm-project/llvm/include/llvm/MC/ |
| D | MCInst.h | 34 class MCOperand {
54 MCOperand() : FPImmVal(0.0) {} in MCOperand() function
115 static MCOperand createReg(unsigned Reg) { in createReg()
116 MCOperand Op; in createReg()
122 static MCOperand createImm(int64_t Val) { in createImm()
123 MCOperand Op; in createImm()
129 static MCOperand createFPImm(double Val) { in createFPImm()
130 MCOperand Op; in createFPImm()
136 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
137 MCOperand Op; in createExpr()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 16 MCOperand MCOp;
32 MCOperand MCOp;
48 MCOperand MCOp;
64 MCOperand MCOp;
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
78 MCOperand MCOp;
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
90 MCOperand MCOp;
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 77 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
82 return MCOperand::createExpr(expr); in createSparcMCOperand()
85 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
90 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
105 return MCOperand::createExpr(expr); in createPCXRelExprOp()
109 MCOperand &Callee, in EmitCall()
119 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
142 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
148 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 73 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
78 return MCOperand::createExpr(expr); in createSparcMCOperand()
81 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
86 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
101 return MCOperand::createExpr(expr); in createPCXRelExprOp()
105 MCOperand &Callee, in EmitCall()
115 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
|
| /external/llvm-project/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 73 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
78 return MCOperand::createExpr(expr); in createSparcMCOperand()
81 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
86 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
101 return MCOperand::createExpr(expr); in createPCXRelExprOp()
105 MCOperand &Callee, in EmitCall()
115 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
126 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
138 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
144 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
|