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Searched refs:MC_SECURITY_CFG1_0 (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_memctrl.c75 tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); in plat_memctrl_tzdram_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t132/
Dtegra_def.h105 #define MC_SECURITY_CFG1_0 U(0x74) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/drivers/memctrl/
Dmemctrl_v1.c93 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); in tegra_memctrl_tzdram_setup()
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h241 #define MC_SECURITY_CFG1_0 U(0x74) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_def.h160 #define MC_SECURITY_CFG1_0 U(0x74) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t194/
Dtegra_def.h97 #define MC_SECURITY_CFG1_0 U(0x74) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_memctrl.c676 tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20); in plat_memctrl_tzdram_setup()
688 val = tegra_mc_read_32(MC_SECURITY_CFG1_0) & MC_SECURITY_SIZE_MB_MASK; in plat_memctrl_tzdram_setup()