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Searched refs:MC_SECURITY_CFG3_0 (Results 1 – 7 of 7) sorted by relevance

/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t194/
Dplat_memctrl.c74 tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); in plat_memctrl_tzdram_setup()
Dplat_trampoline.S135 mov x3, #MC_SECURITY_CFG3_0
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t132/
Dtegra_def.h106 #define MC_SECURITY_CFG3_0 U(0x9BC) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t210/
Dtegra_def.h242 #define MC_SECURITY_CFG3_0 U(0x9BC) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t186/
Dtegra_def.h161 #define MC_SECURITY_CFG3_0 U(0x9BC) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/include/t194/
Dtegra_def.h98 #define MC_SECURITY_CFG3_0 U(0x9BC) macro
/external/arm-trusted-firmware/plat/nvidia/tegra/soc/t186/
Dplat_memctrl.c675 tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); in plat_memctrl_tzdram_setup()
692 val = tegra_mc_read_32(MC_SECURITY_CFG3_0) & MC_SECURITY_BOM_HI_MASK; in plat_memctrl_tzdram_setup()