1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MEMCTRL_V1_H 8 #define MEMCTRL_V1_H 9 10 #include <lib/mmio.h> 11 12 #include <tegra_def.h> 13 14 /* SMMU registers */ 15 #define MC_SMMU_CONFIG_0 0x10U 16 #define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U 17 #define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U 18 #define MC_SMMU_TLB_CONFIG_0 0x14U 19 #define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U 20 #define MC_SMMU_PTC_CONFIG_0 0x18U 21 #define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU 22 #define MC_SMMU_TLB_FLUSH_0 0x30U 23 #define TLB_FLUSH_VA_MATCH_ALL 0U 24 #define TLB_FLUSH_ASID_MATCH_DISABLE 0U 25 #define TLB_FLUSH_ASID_MATCH_SHIFT 31U 26 #define MC_SMMU_TLB_FLUSH_ALL \ 27 (TLB_FLUSH_VA_MATCH_ALL | \ 28 (TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT)) 29 #define MC_SMMU_PTC_FLUSH_0 0x34U 30 #define MC_SMMU_PTC_FLUSH_ALL 0U 31 #define MC_SMMU_ASID_SECURITY_0 0x38U 32 #define MC_SMMU_ASID_SECURITY 0U 33 #define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U 34 #define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU 35 #define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U 36 #define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U 37 #define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U 38 #define MC_SMMU_TRANSLATION_ENABLE (~0) 39 40 /* MC IRAM aperture registers */ 41 #define MC_IRAM_BASE_LO 0x65CU 42 #define MC_IRAM_TOP_LO 0x660U 43 #define MC_IRAM_BASE_TOP_HI 0x980U 44 #define MC_IRAM_REG_CTRL 0x964U 45 #define MC_DISABLE_IRAM_CFG_WRITES 1U 46 tegra_mc_read_32(uint32_t off)47static inline uint32_t tegra_mc_read_32(uint32_t off) 48 { 49 return mmio_read_32(TEGRA_MC_BASE + off); 50 } 51 tegra_mc_write_32(uint32_t off,uint32_t val)52static inline void tegra_mc_write_32(uint32_t off, uint32_t val) 53 { 54 mmio_write_32(TEGRA_MC_BASE + off, val); 55 } 56 57 #endif /* MEMCTRL_V1_H */ 58