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1 /*
2  * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef TEGRA_MC_DEF_H
8 #define TEGRA_MC_DEF_H
9 
10 /*******************************************************************************
11  * Memory Controller's PCFIFO client configuration registers
12  ******************************************************************************/
13 #define MC_PCFIFO_CLIENT_CONFIG0				0xdd0U
14 
15 #define MC_PCFIFO_CLIENT_CONFIG1				0xdd4U
16 #define  MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL			0x20000U
17 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED		(0U << 17)
18 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK		(1U << 17)
19 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED		(0U << 21)
20 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK		(1U << 21)
21 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED 	(0U << 29)
22 #define  MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK		(1U << 29)
23 
24 #define MC_PCFIFO_CLIENT_CONFIG2				0xdd8U
25 #define  MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL			0x20000U
26 #define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED	(0U << 11)
27 #define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK	(1U << 11)
28 #define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED	(0U << 13)
29 #define  MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK		(1U << 13)
30 
31 #define MC_PCFIFO_CLIENT_CONFIG3				0xddcU
32 #define  MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL			0U
33 #define  MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED	(0U << 7)
34 #define  MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK		(1U << 7)
35 
36 #define MC_PCFIFO_CLIENT_CONFIG4				0xde0U
37 #define  MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL			0U
38 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED 	(0U << 1)
39 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK		(1U << 1)
40 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED		(0U << 5)
41 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK		(1U << 5)
42 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED 	(0U << 13)
43 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK		(1U << 13)
44 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED 	(0U << 15)
45 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED 		(1U << 15)
46 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK		(1U << 15)
47 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED	(0U << 17)
48 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK		(1U << 17)
49 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED	(0U << 22)
50 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK		(1U << 22)
51 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED	(0U << 26)
52 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK		(1U << 26)
53 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED	(0U << 30)
54 #define  MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK		(1U << 30)
55 
56 #define MC_PCFIFO_CLIENT_CONFIG5				0xbf4U
57 #define  MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL			0U
58 #define  MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED	(0U << 0)
59 #define  MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK		(1U << 0)
60 
61 /*******************************************************************************
62  * Stream ID Override Config registers
63  ******************************************************************************/
64 #define MC_STREAMID_OVERRIDE_CFG_PTCR				0x000U
65 #define MC_STREAMID_OVERRIDE_CFG_AFIR				0x070U
66 #define MC_STREAMID_OVERRIDE_CFG_HDAR				0x0A8U
67 #define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR			0x0B0U
68 #define MC_STREAMID_OVERRIDE_CFG_NVENCSRD			0x0E0U
69 #define MC_STREAMID_OVERRIDE_CFG_SATAR				0x0F8U
70 #define MC_STREAMID_OVERRIDE_CFG_MPCORER			0x138U
71 #define MC_STREAMID_OVERRIDE_CFG_NVENCSWR			0x158U
72 #define MC_STREAMID_OVERRIDE_CFG_AFIW				0x188U
73 #define MC_STREAMID_OVERRIDE_CFG_HDAW				0x1A8U
74 #define MC_STREAMID_OVERRIDE_CFG_MPCOREW			0x1C8U
75 #define MC_STREAMID_OVERRIDE_CFG_SATAW				0x1E8U
76 #define MC_STREAMID_OVERRIDE_CFG_ISPRA				0x220U
77 #define MC_STREAMID_OVERRIDE_CFG_ISPWA				0x230U
78 #define MC_STREAMID_OVERRIDE_CFG_ISPWB				0x238U
79 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR			0x250U
80 #define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW			0x258U
81 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR			0x260U
82 #define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW			0x268U
83 #define MC_STREAMID_OVERRIDE_CFG_TSECSRD			0x2A0U
84 #define MC_STREAMID_OVERRIDE_CFG_TSECSWR			0x2A8U
85 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD				0x2C0U
86 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR				0x2C8U
87 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRA			0x300U
88 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA			0x308U
89 #define MC_STREAMID_OVERRIDE_CFG_SDMMCR				0x310U
90 #define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB			0x318U
91 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWA			0x320U
92 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA			0x328U
93 #define MC_STREAMID_OVERRIDE_CFG_SDMMCW				0x330U
94 #define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB			0x338U
95 #define MC_STREAMID_OVERRIDE_CFG_VICSRD				0x360U
96 #define MC_STREAMID_OVERRIDE_CFG_VICSWR				0x368U
97 #define MC_STREAMID_OVERRIDE_CFG_VIW				0x390U
98 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD			0x3C0U
99 #define MC_STREAMID_OVERRIDE_CFG_NVDECSWR			0x3C8U
100 #define MC_STREAMID_OVERRIDE_CFG_APER				0x3D0U
101 #define MC_STREAMID_OVERRIDE_CFG_APEW				0x3D8U
102 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD			0x3F0U
103 #define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR			0x3F8U
104 #define MC_STREAMID_OVERRIDE_CFG_SESRD				0x400U
105 #define MC_STREAMID_OVERRIDE_CFG_SESWR				0x408U
106 #define MC_STREAMID_OVERRIDE_CFG_ETRR				0x420U
107 #define MC_STREAMID_OVERRIDE_CFG_ETRW				0x428U
108 #define MC_STREAMID_OVERRIDE_CFG_TSECSRDB			0x430U
109 #define MC_STREAMID_OVERRIDE_CFG_TSECSWRB			0x438U
110 #define MC_STREAMID_OVERRIDE_CFG_GPUSRD2			0x440U
111 #define MC_STREAMID_OVERRIDE_CFG_GPUSWR2			0x448U
112 #define MC_STREAMID_OVERRIDE_CFG_AXISR				0x460U
113 #define MC_STREAMID_OVERRIDE_CFG_AXISW				0x468U
114 #define MC_STREAMID_OVERRIDE_CFG_EQOSR				0x470U
115 #define MC_STREAMID_OVERRIDE_CFG_EQOSW				0x478U
116 #define MC_STREAMID_OVERRIDE_CFG_UFSHCR				0x480U
117 #define MC_STREAMID_OVERRIDE_CFG_UFSHCW				0x488U
118 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR			0x490U
119 #define MC_STREAMID_OVERRIDE_CFG_BPMPR				0x498U
120 #define MC_STREAMID_OVERRIDE_CFG_BPMPW				0x4A0U
121 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR			0x4A8U
122 #define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW			0x4B0U
123 #define MC_STREAMID_OVERRIDE_CFG_AONR				0x4B8U
124 #define MC_STREAMID_OVERRIDE_CFG_AONW				0x4C0U
125 #define MC_STREAMID_OVERRIDE_CFG_AONDMAR			0x4C8U
126 #define MC_STREAMID_OVERRIDE_CFG_AONDMAW			0x4D0U
127 #define MC_STREAMID_OVERRIDE_CFG_SCER				0x4D8U
128 #define MC_STREAMID_OVERRIDE_CFG_SCEW				0x4E0U
129 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAR			0x4E8U
130 #define MC_STREAMID_OVERRIDE_CFG_SCEDMAW			0x4F0U
131 #define MC_STREAMID_OVERRIDE_CFG_APEDMAR			0x4F8U
132 #define MC_STREAMID_OVERRIDE_CFG_APEDMAW			0x500U
133 #define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1			0x508U
134 #define MC_STREAMID_OVERRIDE_CFG_VICSRD1			0x510U
135 #define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1			0x518U
136 
137 /*******************************************************************************
138  * Macro to calculate Security cfg register addr from StreamID Override register
139  ******************************************************************************/
140 #define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
141 
142 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV		(0U << 4)
143 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV	(1U << 4)
144 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV		(2U << 4)
145 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV	(3U << 4)
146 
147 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL		(0U << 8)
148 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL	(1U << 8)
149 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL		(2U << 8)
150 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL	(3U << 8)
151 
152 #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO				(0U << 12)
153 #define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID		(1U << 12)
154 
155 /*******************************************************************************
156  * Memory Controller transaction override config registers
157  ******************************************************************************/
158 #define MC_TXN_OVERRIDE_CONFIG_HDAR				0x10a8U
159 #define MC_TXN_OVERRIDE_CONFIG_BPMPW				0x14a0U
160 #define MC_TXN_OVERRIDE_CONFIG_PTCR				0x1000U
161 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR			0x1490U
162 #define MC_TXN_OVERRIDE_CONFIG_EQOSW				0x1478U
163 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR				0x13f8U
164 #define MC_TXN_OVERRIDE_CONFIG_ISPRA				0x1220U
165 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA				0x1328U
166 #define MC_TXN_OVERRIDE_CONFIG_VICSRD				0x1360U
167 #define MC_TXN_OVERRIDE_CONFIG_MPCOREW				0x11c8U
168 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD				0x12c0U
169 #define MC_TXN_OVERRIDE_CONFIG_AXISR				0x1460U
170 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAW				0x14f0U
171 #define MC_TXN_OVERRIDE_CONFIG_SDMMCW				0x1330U
172 #define MC_TXN_OVERRIDE_CONFIG_EQOSR				0x1470U
173 #define MC_TXN_OVERRIDE_CONFIG_APEDMAR				0x14f8U
174 #define MC_TXN_OVERRIDE_CONFIG_NVENCSRD				0x10e0U
175 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB				0x1318U
176 #define MC_TXN_OVERRIDE_CONFIG_VICSRD1				0x1510U
177 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR				0x14a8U
178 #define MC_TXN_OVERRIDE_CONFIG_VIW				0x1390U
179 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA				0x1308U
180 #define MC_TXN_OVERRIDE_CONFIG_AXISW				0x1468U
181 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR			0x1260U
182 #define MC_TXN_OVERRIDE_CONFIG_UFSHCR				0x1480U
183 #define MC_TXN_OVERRIDE_CONFIG_TSECSWR				0x12a8U
184 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR				0x12c8U
185 #define MC_TXN_OVERRIDE_CONFIG_SATAR				0x10f8U
186 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW			0x1258U
187 #define MC_TXN_OVERRIDE_CONFIG_TSECSWRB				0x1438U
188 #define MC_TXN_OVERRIDE_CONFIG_GPUSRD2				0x1440U
189 #define MC_TXN_OVERRIDE_CONFIG_SCEDMAR				0x14e8U
190 #define MC_TXN_OVERRIDE_CONFIG_GPUSWR2				0x1448U
191 #define MC_TXN_OVERRIDE_CONFIG_AONDMAW				0x14d0U
192 #define MC_TXN_OVERRIDE_CONFIG_APEDMAW				0x1500U
193 #define MC_TXN_OVERRIDE_CONFIG_AONW				0x14c0U
194 #define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR			0x10b0U
195 #define MC_TXN_OVERRIDE_CONFIG_ETRR				0x1420U
196 #define MC_TXN_OVERRIDE_CONFIG_SESWR				0x1408U
197 #define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD				0x13f0U
198 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD				0x13c0U
199 #define MC_TXN_OVERRIDE_CONFIG_TSECSRDB				0x1430U
200 #define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW				0x14b0U
201 #define MC_TXN_OVERRIDE_CONFIG_APER				0x13d0U
202 #define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1			0x1518U
203 #define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR			0x1250U
204 #define MC_TXN_OVERRIDE_CONFIG_ISPWA				0x1230U
205 #define MC_TXN_OVERRIDE_CONFIG_SESRD				0x1400U
206 #define MC_TXN_OVERRIDE_CONFIG_SCER				0x14d8U
207 #define MC_TXN_OVERRIDE_CONFIG_AONR				0x14b8U
208 #define MC_TXN_OVERRIDE_CONFIG_MPCORER				0x1138U
209 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWA				0x1320U
210 #define MC_TXN_OVERRIDE_CONFIG_HDAW				0x11a8U
211 #define MC_TXN_OVERRIDE_CONFIG_NVDECSWR				0x13c8U
212 #define MC_TXN_OVERRIDE_CONFIG_UFSHCW				0x1488U
213 #define MC_TXN_OVERRIDE_CONFIG_AONDMAR				0x14c8U
214 #define MC_TXN_OVERRIDE_CONFIG_SATAW				0x11e8U
215 #define MC_TXN_OVERRIDE_CONFIG_ETRW				0x1428U
216 #define MC_TXN_OVERRIDE_CONFIG_VICSWR				0x1368U
217 #define MC_TXN_OVERRIDE_CONFIG_NVENCSWR				0x1158U
218 #define MC_TXN_OVERRIDE_CONFIG_AFIR				0x1070U
219 #define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB				0x1338U
220 #define MC_TXN_OVERRIDE_CONFIG_SDMMCRA				0x1300U
221 #define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1			0x1508U
222 #define MC_TXN_OVERRIDE_CONFIG_ISPWB				0x1238U
223 #define MC_TXN_OVERRIDE_CONFIG_BPMPR				0x1498U
224 #define MC_TXN_OVERRIDE_CONFIG_APEW				0x13d8U
225 #define MC_TXN_OVERRIDE_CONFIG_SDMMCR				0x1310U
226 #define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW			0x1268U
227 #define MC_TXN_OVERRIDE_CONFIG_TSECSRD				0x12a0U
228 #define MC_TXN_OVERRIDE_CONFIG_AFIW				0x1188U
229 #define MC_TXN_OVERRIDE_CONFIG_SCEW				0x14e0U
230 
231 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID			(1U << 0)
232 #define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV			(2U << 4)
233 #define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT	(1U << 12)
234 
235 /*******************************************************************************
236  * Non-SO_DEV transactions override values for CGID_TAG bitfield for the
237  * MC_TXN_OVERRIDE_CONFIG_{module} registers
238  ******************************************************************************/
239 #define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT			0U
240 #define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID			1U
241 #define MC_TXN_OVERRIDE_CGID_TAG_ZERO				2U
242 #define MC_TXN_OVERRIDE_CGID_TAG_ADR				3U
243 #define MC_TXN_OVERRIDE_CGID_TAG_MASK				3ULL
244 
245 /*******************************************************************************
246  * Memory Controller Reset Control registers
247  ******************************************************************************/
248 #define MC_CLIENT_HOTRESET_CTRL0				0x200U
249 #define  MC_CLIENT_HOTRESET_CTRL0_RESET_VAL			0U
250 #define  MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB			(1U << 0)
251 #define  MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB			(1U << 6)
252 #define  MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB			(1U << 7)
253 #define  MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB		(1U << 8)
254 #define  MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB		(1U << 9)
255 #define  MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB		(1U << 11)
256 #define  MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB		(1U << 15)
257 #define  MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB			(1U << 17)
258 #define  MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB			(1U << 18)
259 #define  MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB		(1U << 19)
260 #define  MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB		(1U << 20)
261 #define  MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB		(1U << 22)
262 #define  MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB		(1U << 29)
263 #define  MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB		(1U << 30)
264 #define  MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB		(1U << 31)
265 #define MC_CLIENT_HOTRESET_STATUS0				0x204U
266 #define MC_CLIENT_HOTRESET_CTRL1				0x970U
267 #define  MC_CLIENT_HOTRESET_CTRL1_RESET_VAL			0U
268 #define  MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB		(1U << 0)
269 #define  MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB			(1U << 2)
270 #define  MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB		(1U << 5)
271 #define  MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB			(1U << 6)
272 #define  MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB			(1U << 7)
273 #define  MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB		(1U << 8)
274 #define  MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB			(1U << 12)
275 #define  MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB		(1U << 13)
276 #define  MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB		(1U << 18)
277 #define  MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB		(1U << 19)
278 #define  MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB		(1U << 20)
279 #define  MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB		(1U << 21)
280 #define  MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB		(1U << 22)
281 #define  MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB			(1U << 23)
282 #define  MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB			(1U << 24)
283 #define MC_CLIENT_HOTRESET_STATUS1				0x974U
284 
285 #ifndef __ASSEMBLER__
286 
287 /*******************************************************************************
288  * Structure to hold the transaction override settings to use to override
289  * client inputs
290  ******************************************************************************/
291 typedef struct mc_txn_override_cfg {
292 	uint32_t offset;
293 	uint8_t cgid_tag;
294 } mc_txn_override_cfg_t;
295 
296 #define mc_make_txn_override_cfg(off, val) \
297 	{ \
298 		.offset = MC_TXN_OVERRIDE_CONFIG_ ## off, \
299 		.cgid_tag = MC_TXN_OVERRIDE_ ## val \
300 	}
301 
302 /*******************************************************************************
303  * Structure to hold the Stream ID to use to override client inputs
304  ******************************************************************************/
305 typedef struct mc_streamid_override_cfg {
306 	uint32_t offset;
307 	uint8_t stream_id;
308 } mc_streamid_override_cfg_t;
309 
310 /*******************************************************************************
311  * Structure to hold the Stream ID Security Configuration settings
312  ******************************************************************************/
313 typedef struct mc_streamid_security_cfg {
314 	char *name;
315 	uint32_t offset;
316 	uint32_t override_enable;
317 	uint32_t override_client_inputs;
318 	uint32_t override_client_ns_flag;
319 } mc_streamid_security_cfg_t;
320 
321 #define OVERRIDE_DISABLE				1U
322 #define OVERRIDE_ENABLE					0U
323 #define CLIENT_FLAG_SECURE				0U
324 #define CLIENT_FLAG_NON_SECURE				1U
325 #define CLIENT_INPUTS_OVERRIDE				1U
326 #define CLIENT_INPUTS_NO_OVERRIDE			0U
327 
328 /*******************************************************************************
329  * StreamID to indicate no SMMU translations (requests to be steered on the
330  * SMMU bypass path)
331  ******************************************************************************/
332 #define MC_STREAM_ID_MAX			0x7FU
333 
334 #define mc_make_sec_cfg(off, ns, ovrrd, access) \
335 	{ \
336 		.name = # off, \
337 		.offset = MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
338 				MC_STREAMID_OVERRIDE_CFG_ ## off), \
339 		.override_client_ns_flag = CLIENT_FLAG_ ## ns, \
340 		.override_client_inputs = CLIENT_INPUTS_ ## ovrrd, \
341 		.override_enable = OVERRIDE_ ## access \
342 	}
343 
344 #define mc_make_sid_override_cfg(name) \
345 	{ \
346 		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
347 		.val = 0x00000000U, \
348 	}
349 
350 #define mc_make_sid_security_cfg(name) \
351 	{ \
352 		.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
353 		.val = 0x00000000U, \
354 	}
355 
356 #define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
357 	((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
358 	 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
359 
360 #define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
361 	 MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_ORDERED
362 
363 #define mc_set_tsa_passthrough(client) \
364 	do { \
365 		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
366 			(TSA_CONFIG_STATIC0_CSW_##client##_RESET & \
367 			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
368 			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
369 	} while (0)
370 
371 #define mc_set_tsa_w_passthrough(client) \
372 	do { \
373 		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
374 			(TSA_CONFIG_STATIC0_CSW_RESET_W & \
375 			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
376 			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
377 	} while (0)
378 
379 #define mc_set_tsa_r_passthrough(client) \
380 	{ \
381 		mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
382 			(TSA_CONFIG_STATIC0_CSR_RESET_R & \
383 			 (uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
384 			(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
385 	} while (0)
386 
387 #define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
388 	do { \
389 		tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
390 				  MC_TXN_OVERRIDE_##normal_axi_id | \
391 				  MC_TXN_OVERRIDE_CONFIG_COH_PATH_##so_dev_override##_SO_DEV | \
392 				  MC_TXN_OVERRIDE_CONFIG_COH_PATH_##normal_override##_NORMAL | \
393 				  MC_TXN_OVERRIDE_CONFIG_CGID_##so_dev_axi_id); \
394 	} while (0)
395 
396 #endif /* __ASSEMBLER__ */
397 
398 #endif /* TEGRA_MC_DEF_H */
399