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Searched refs:MD_CONTEXT_MIPS_REG_S0 (Results 1 – 5 of 5) sorted by relevance

/external/google-breakpad/src/google_breakpad/common/
Dminidump_cpu_mips.h125 MD_CONTEXT_MIPS_REG_S0 = 16, enumerator
/external/google-breakpad/src/processor/
Dstackwalker_mips_unittest.cc544 expected.iregs[MD_CONTEXT_MIPS_REG_S0] = 0x0; in CFIFixture()
610 EXPECT_EQ(expected.iregs[MD_CONTEXT_MIPS_REG_S0], in CheckWalk()
611 frame1->context.iregs[MD_CONTEXT_MIPS_REG_S0]); in CheckWalk()
Dstackwalker_mips64_unittest.cc552 expected.iregs[MD_CONTEXT_MIPS_REG_S0] = 0x0; in CFIFixture()
619 EXPECT_EQ(expected.iregs[MD_CONTEXT_MIPS_REG_S0], in CheckWalk()
620 frame1->context.iregs[MD_CONTEXT_MIPS_REG_S0]); in CheckWalk()
Dstackwalk_common.cc575 frame_mips->context.iregs[MD_CONTEXT_MIPS_REG_S0], in PrintStack()
/external/google-breakpad/src/google_breakpad/processor/
Dstack_frame_cpu.h346 #define INDEX_MIPS_REG_S0 MD_CONTEXT_MIPS_REG_S0 // 16