/external/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 192 MERGE_VALUES, enumerator
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 199 MERGE_VALUES, enumerator
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/external/llvm-project/llvm/include/llvm/CodeGen/ |
D | ISDOpcodes.h | 229 MERGE_VALUES, enumerator
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/external/llvm-project/llvm/utils/ |
D | update_mir_test_checks.py | 254 MERGE_VALUES='MV',
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 146 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
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D | InstrEmitter.cpp | 894 case ISD::MERGE_VALUES: in EmitSpecialNode()
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D | SelectionDAGBuilder.cpp | 738 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs() 2375 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad() 2842 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect() 3243 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue() 3277 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue() 3555 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad() 7774 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo()
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D | LegalizeFloatTypes.cpp | 70 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult() 1008 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
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D | LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult() 589 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in SplitVectorResult() 2057 case ISD::MERGE_VALUES: Res = WidenVecRes_MERGE_VALUES(N, ResNo); break; in WidenVectorResult()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | LegalizeVectorOps.cpp | 331 case ISD::MERGE_VALUES: in LegalizeOp() 725 case ISD::MERGE_VALUES: in Expand()
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D | SelectionDAGDumper.cpp | 175 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
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D | SelectionDAGBuilder.cpp | 872 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs() 2910 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad() 3251 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect() 3665 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue() 3705 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue() 4024 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad() 8607 if (Val.getOpcode() == ISD::MERGE_VALUES) { in visitInlineAsm() 8623 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInlineAsm() 9492 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo() 10785 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitFreeze()
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D | InstrEmitter.cpp | 1074 case ISD::MERGE_VALUES: in EmitSpecialNode()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | SelectionDAGDumper.cpp | 173 case ISD::MERGE_VALUES: return "merge_values"; in getOperationName()
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D | LegalizeVectorOps.cpp | 335 case ISD::MERGE_VALUES: in LegalizeOp() 844 case ISD::MERGE_VALUES: in Expand()
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D | SelectionDAGBuilder.cpp | 887 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values); in getCopyFromRegs() 2933 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, in visitLandingPad() 3412 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitSelect() 3828 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInsertValue() 3868 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitExtractValue() 4162 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, dl, in visitLoad() 8540 if (Val.getOpcode() == ISD::MERGE_VALUES) { in visitInlineAsm() 8556 SDValue V = DAG.getNode(ISD::MERGE_VALUES, getCurSDLoc(), in visitInlineAsm() 9406 SDValue Res = CLI.DAG.getNode(ISD::MERGE_VALUES, CLI.DL, in LowerCallTo()
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D | InstrEmitter.cpp | 991 case ISD::MERGE_VALUES: in EmitSpecialNode()
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D | LegalizeFloatTypes.cpp | 61 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult() 1121 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 1644 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD() 1645 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 824 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts() 862 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts() 880 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 829 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts() 867 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts() 885 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 1721 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD() 1722 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
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/external/llvm/lib/Target/AMDGPU/ |
D | R600ISelLowering.cpp | 998 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts() 1036 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts() 1054 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT, VT), Res, OVF); in LowerUADDSUBO()
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/external/llvm-project/llvm/lib/CodeGen/ |
D | TargetLoweringBase.cpp | 1830 case ExtractValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD() 1831 case InsertValue: return ISD::MERGE_VALUES; in InstructionOpcodeToISD()
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonISelLoweringHVX.cpp | 2124 assert(S->getOpcode() == ISD::MERGE_VALUES); in LowerHvxOperationWrapper() 2159 assert(Load->getOpcode() == ISD::MERGE_VALUES); in ReplaceHvxNodeResults()
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