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Searched refs:MFC1 (Results 1 – 25 of 35) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/
Dfptosi_and_fptoui.mir24 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
31 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_S]]
54 ; FP32: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D32_]]
61 ; FP64: [[MFC1_:%[0-9]+]]:gpr32 = MFC1 [[TRUNC_W_D64_]]
/external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/
Dfptosi.ll46 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
57 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
99 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
111 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
122 ; M64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
134 ; M64R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
237 ; M32-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
248 ; M32R2-FP64-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
290 ; M32R3R5-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
302 ; M32R6-NEXT: mfc1 $2, $f0 # <MCInst #{{[0-9]+}} MFC1
[all …]
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
848 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
DMipsSEInstrInfo.cpp95 Opc = Mips::MFC1; in copyPhysReg()
644 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
DMipsInstrFPU.td366 def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
DMipsFastISel.cpp1080 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
956 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
DMipsSEInstrInfo.cpp99 Opc = Mips::MFC1; in copyPhysReg()
821 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
DMipsInstructionSelector.cpp657 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
DMipsScheduleP5600.td574 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
DMipsInstrFPU.td558 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
DMipsFastISel.cpp1131 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
DMipsScheduleGeneric.td871 MFC1, MFC1_D64, MFHC1_D32,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsAsmPrinter.cpp923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
956 unsigned MovOpc = Mips::MFC1; in EmitSwapFPIntRetval()
DMipsSEInstrInfo.cpp99 Opc = Mips::MFC1; in copyPhysReg()
807 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); in expandExtractElementF64()
DMipsRegisterBankInfo.cpp135 case Mips::MFC1: in isFloatingPointOpcodeUse()
DMipsCallLowering.cpp275 MIRBuilder.buildInstr(Mips::MFC1) in assignValueToReg()
DMipsInstructionSelector.cpp558 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1)) in select()
DMipsScheduleP5600.td573 MFC1, MFC1_D64, MFHC1_D32, MFHC1_D64,
DMipsInstrFPU.td525 def MFC1 : MMRel, StdMMR6Rel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1,
DMipsFastISel.cpp1133 emitInst(Mips::MFC1, DestReg).addReg(TempReg); in selectFPToInt()
DMipsScheduleGeneric.td868 MFC1, MFC1_D64, MFHC1_D32,
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c210 #define MFC1 (HI(17)) macro
1544 return push_inst(compiler, MFC1 | flags | T(dst) | FS(TMP_FREG1), MOVABLE_INS); in sljit_emit_fop1_conv_sw_from_f64()
2146 FAIL_IF(push_inst(compiler, MFC1 | TA(dst_ar) | FS(TMP_FREG3), dst_ar)); in sljit_emit_op_flags()
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc1093 16451U, // MFC1
2882 0U, // MFC1
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc1926 UINT64_C(1140850688), // MFC1
6665 case Mips::MFC1:
11388 CEFBS_HasStdEnc_IsNotSoftFloat_NotInMicroMips, // MFC1 = 1913

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