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Searched refs:MFHI (Results 1 – 25 of 45) sorted by relevance

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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
232 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
346 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in expandPostRAPseudo()
DMipsDSPInstrFormats.td254 // MFHI sub-class format.
DMipsISelLowering.h77 MFHI, enumerator
DMipsSEISelLowering.cpp449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); in selectMADD()
521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); in selectMSUB()
1286 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1305 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
DMipsSEFrameLowering.cpp800 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
DMipsFastISel.cpp1697 ? Mips::MFHI in selectDivRem()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
418 expandPseudoMFHiLo(MBB, MI, Mips::MFHI); in expandPostRAPseudo()
DMipsDSPInstrFormats.td253 // MFHI sub-class format.
DMipsISelLowering.h127 MFHI, enumerator
DMipsSEFrameLowering.cpp822 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
DMipsScheduleP5600.td181 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
DMipsFastISel.cpp1954 ? Mips::MFHI in selectDivRem()
DMipsSEISelLowering.cpp1278 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1297 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
/external/llvm-project/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; in copyPhysReg()
299 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); in storeRegToStack()
418 expandPseudoMFHiLo(MBB, MI, Mips::MFHI); in expandPostRAPseudo()
DMipsDSPInstrFormats.td253 // MFHI sub-class format.
DMipsISelLowering.h125 MFHI, enumerator
DMipsSEFrameLowering.cpp821 Op = (Reg == Mips::HI0) ? Mips::MFHI : Mips::MFLO; in spillCalleeSavedRegisters()
DMipsScheduleP5600.td182 def : InstRW<[P5600WriteAL2], (instrs CLO, CLZ, DI, EI, MFHI, MFLO,
DMipsFastISel.cpp1952 ? Mips::MFHI in selectDivRem()
DMipsSEISelLowering.cpp1278 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); in lowerMulDiv()
1297 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); in extractLOHI()
/external/pcre/dist2/src/sljit/
DsljitNativeMIPS_common.c215 #define MFHI (HI(0) | LO(16)) macro
1255 return push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)); in sljit_emit_op0()
1292 …return (op >= SLJIT_DIV_UW) ? SLJIT_SUCCESS : push_inst(compiler, MFHI | D(SLJIT_R1), DR(SLJIT_R1)… in sljit_emit_op0()
DsljitNativeMIPS_32.c384 FAIL_IF(push_inst(compiler, MFHI | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
DsljitNativeMIPS_64.c480 FAIL_IF(push_inst(compiler, MFHI | DA(EQUAL_FLAG), EQUAL_FLAG)); in emit_single_op()
/external/llvm-project/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4242 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4291 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4329 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
5197 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5234 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp4214 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4263 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
4301 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI); in expandDivRem()
5087 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulO()
5124 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI); in expandMulOU()

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