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/external/capstone/arch/X86/
DX86IntelInstPrinter.c56 static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
57 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
60 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
62 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
65 MI->csh->doing_mem = status; in set_mem_access()
68 MI->flat_insn->detail->x86.op_count++; in set_mem_access()
72 static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) in printopaquemem() argument
76 switch(MI->flat_insn->id) { in printopaquemem()
92 switch(MI->csh->mode) { in printopaquemem()
94 switch(MI->flat_insn->id) { in printopaquemem()
[all …]
DX86ATTInstPrinter.c56 static void printMemReference(MCInst *MI, unsigned Op, SStream *O);
57 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
60 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
62 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
65 MI->csh->doing_mem = status; in set_mem_access()
68 MI->flat_insn->detail->x86.op_count++; in set_mem_access()
71 static void printopaquemem(MCInst *MI, unsigned OpNo, SStream *O) in printopaquemem() argument
73 switch(MI->csh->mode) { in printopaquemem()
75 switch(MI->flat_insn->id) { in printopaquemem()
77 MI->x86opsize = 2; in printopaquemem()
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/external/capstone/arch/ARM/
DARMInstPrinter.c41 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
42 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
43 static void printSORegRegOperand(MCInst *MI, unsigned OpNum, SStream *O);
44 static void printSORegImmOperand(MCInst *MI, unsigned OpNum, SStream *O);
46 static void printAddrModeTBB(MCInst *MI, unsigned OpNum, SStream *O);
47 static void printAddrModeTBH(MCInst *MI, unsigned OpNum, SStream *O);
48 static void printAddrMode2Operand(MCInst *MI, unsigned OpNum, SStream *O);
49 static void printAM2PreOrOffsetIndexOp(MCInst *MI, unsigned OpNum, SStream *O);
50 static void printAddrMode2OffsetOperand(MCInst *MI, unsigned OpNum, SStream *O);
51 static void printAddrMode3Operand(MCInst *MI, unsigned OpNum, SStream *O, bool AlwaysPrintImm0);
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/external/capstone/arch/AArch64/
DAArch64InstPrinter.c42 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
43 static bool printSysAlias(MCInst *MI, SStream *O);
44 static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
45 static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
46 static void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
62 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
64 MI->csh->doing_mem = status; in set_mem_access()
66 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
72 access = get_op_access(MI->csh, MCInst_getOpcode(MI), MI->ac_idx); in set_mem_access()
73 MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].access = access; in set_mem_access()
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/external/capstone/arch/SystemZ/
DSystemZInstPrinter.c42 static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O) in printAddress() argument
52 if (MI->csh->detail) { in printAddress()
53 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_MEM; in printAddress()
54 …MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.base = (uint8_t)Sys… in printAddress()
55 …MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.index = (uint8_t)Sy… in printAddress()
56 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp; in printAddress()
57 MI->flat_insn->detail->sysz.op_count++; in printAddress()
60 if (MI->csh->detail) { in printAddress()
61 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].type = SYSZ_OP_IMM; in printAddress()
62 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].imm = Disp; in printAddress()
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/external/capstone/arch/PowerPC/
DPPCInstPrinter.c36 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
37 static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
38 static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
39 static char *printAliasInstr(MCInst *MI, SStream *OS, void *info);
40 static char *printAliasInstrEx(MCInst *MI, SStream *OS, void *info);
41 static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
60 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
62 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
65 MI->csh->doing_mem = status; in set_mem_access()
68 MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM; in set_mem_access()
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/external/capstone/arch/Sparc/
DSparcGenAsmWriter.inc18 static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
830 uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
847 printOperand(MI, 1, O);
851 printOperand(MI, 0, O);
855 printCCOperand(MI, 1, O);
859 printMemOperand(MI, 0, O, NULL);
864 printCCOperand(MI, 3, O);
868 printGetPCX(MI, 0, O);
873 printMemOperand(MI, 1, O, NULL);
877 printMemOperand(MI, 1, O, "arith");
[all …]
DSparcInstPrinter.c43 static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
44 static void printMemOperand(MCInst *MI, int opNum, SStream *O, const char *Modifier);
45 static void printOperand(MCInst *MI, int opNum, SStream *O);
47 static void Sparc_add_hint(MCInst *MI, unsigned int hint) in Sparc_add_hint() argument
49 if (MI->csh->detail) { in Sparc_add_hint()
50 MI->flat_insn->detail->sparc.hint = hint; in Sparc_add_hint()
54 static void Sparc_add_reg(MCInst *MI, unsigned int reg) in Sparc_add_reg() argument
56 if (MI->csh->detail) { in Sparc_add_reg()
57 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].type = SPARC_OP_REG; in Sparc_add_reg()
58 MI->flat_insn->detail->sparc.operands[MI->flat_insn->detail->sparc.op_count].reg = reg; in Sparc_add_reg()
[all …]
/external/capstone/arch/Mips/
DMipsInstPrinter.c33 static void printUnsignedImm(MCInst *MI, int opNum, SStream *O);
34 static char *printAliasInstr(MCInst *MI, SStream *O, void *info);
35 static char *printAlias(MCInst *MI, SStream *OS);
86 static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI);
88 static void set_mem_access(MCInst *MI, bool status) in set_mem_access() argument
90 MI->csh->doing_mem = status; in set_mem_access()
92 if (MI->csh->detail != CS_OPT_ON) in set_mem_access()
96 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].type = MIPS_OP_MEM; in set_mem_access()
97 …MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.base = MIPS_REG_INV… in set_mem_access()
98 MI->flat_insn->detail->mips.operands[MI->flat_insn->detail->mips.op_count].mem.disp = 0; in set_mem_access()
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/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DCombinerHelper.h42 MachineInstr *MI; member
123 bool tryCombineCopy(MachineInstr &MI);
124 bool matchCombineCopy(MachineInstr &MI);
125 void applyCombineCopy(MachineInstr &MI);
141 bool tryCombineExtendingLoads(MachineInstr &MI);
142 bool matchCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
143 void applyCombineExtendingLoads(MachineInstr &MI, PreferredTuple &MatchInfo);
147 bool tryCombineIndexedLoadStore(MachineInstr &MI);
148 bool matchCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
149 void applyCombineIndexedLoadStore(MachineInstr &MI, IndexedLoadStoreMatchInfo &MatchInfo);
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/external/capstone/arch/XCore/
DXCoreInstPrinter.c48 void XCore_insn_extract(MCInst *MI, const char *code) in XCore_insn_extract() argument
67 if (MI->csh->detail) { in XCore_insn_extract()
68 … MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_REG; in XCore_insn_extract()
69 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].reg = id; in XCore_insn_extract()
70 MI->flat_insn->detail->xcore.op_count++; in XCore_insn_extract()
89 if (MI->csh->detail) { in XCore_insn_extract()
90 … MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].type = XCORE_OP_MEM; in XCore_insn_extract()
91 …MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.base = (uint8_t)i… in XCore_insn_extract()
92 …MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.index = XCORE_REG… in XCore_insn_extract()
93 MI->flat_insn->detail->xcore.operands[MI->flat_insn->detail->xcore.op_count].mem.disp = 0; in XCore_insn_extract()
[all …]
/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp43 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
49 bool shortenFusedFPOp(MachineInstr &MI, unsigned Opcode);
67 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
68 if (MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) == 0 && in tieOpsIfNeeded()
69 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86ATTInstPrinter.h28 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
44 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
45 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
46 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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DX86IntelInstPrinter.h29 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot,
33 void printInstruction(const MCInst *MI, raw_ostream &O);
36 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
37 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
38 void printSSEAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printXOPCC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
41 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
43 void printDstIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp43 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
44 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
45 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
48 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
66 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
67 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
68 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
69 MI.tieOperands(0, 1); in tieOpsIfNeeded()
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/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h46 unsigned isLoadFromStackSlot(const MachineInstr &MI,
54 unsigned isStoreToStackSlot(const MachineInstr &MI,
189 bool expandPostRAPseudo(MachineInstr &MI) const override;
203 MachineBasicBlock::iterator MI) const override;
206 bool isPredicated(const MachineInstr &MI) const override;
210 bool PredicateInstruction(MachineInstr &MI,
221 bool DefinesPredicate(MachineInstr &MI,
227 bool isPredicable(MachineInstr &MI) const override;
231 bool isSchedulingBoundary(const MachineInstr &MI,
250 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DGCNHazardRecognizer.cpp61 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction() argument
62 CurrCycleInstr = MI; in EmitInstruction()
105 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS() argument
106 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
109 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
120 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
121 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
123 if (MI.getOperand(GDS).getImm()) in isSendMsgTraceDataOrGDS()
130 static bool isPermlane(const MachineInstr &MI) { in isPermlane() argument
131 unsigned Opcode = MI.getOpcode(); in isPermlane()
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/external/llvm-project/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitOperands(MachineInstr *MI);
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) { in TransferImplicitOperands() argument
68 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitOperands()
71 for (const MachineOperand &MO : MI->implicit_operands()) in TransferImplicitOperands()
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
77 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
78 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
79 MI->getOperand(1).isImm() && in LowerSubregToReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitOperands(MachineInstr *MI);
67 void ExpandPostRA::TransferImplicitOperands(MachineInstr *MI) { in TransferImplicitOperands() argument
68 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitOperands()
71 for (const MachineOperand &MO : MI->implicit_operands()) in TransferImplicitOperands()
76 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
77 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
78 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
79 MI->getOperand(1).isImm() && in LowerSubregToReg()
[all …]
/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp51 bool LowerSubregToReg(MachineInstr *MI);
52 bool LowerCopy(MachineInstr *MI);
54 void TransferImplicitDefs(MachineInstr *MI);
68 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
69 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
72 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
73 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
80 bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) { in LowerSubregToReg() argument
81 MachineBasicBlock *MBB = MI->getParent(); in LowerSubregToReg()
82 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
219 MachineBasicBlock::iterator MI) const override;
222 bool isPredicated(const MachineInstr &MI) const override;
225 bool isPostIncrement(const MachineInstr &MI) const override;
229 bool PredicateInstruction(MachineInstr &MI,
240 bool DefinesPredicate(MachineInstr &MI,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DGCNHazardRecognizer.cpp57 void GCNHazardRecognizer::EmitInstruction(MachineInstr *MI) { in EmitInstruction() argument
58 CurrCycleInstr = MI; in EmitInstruction()
94 const MachineInstr &MI) { in isSendMsgTraceDataOrGDS() argument
95 if (TII.isAlwaysGDS(MI.getOpcode())) in isSendMsgTraceDataOrGDS()
98 switch (MI.getOpcode()) { in isSendMsgTraceDataOrGDS()
109 if (TII.isDS(MI.getOpcode())) { in isSendMsgTraceDataOrGDS()
110 int GDS = AMDGPU::getNamedOperandIdx(MI.getOpcode(), in isSendMsgTraceDataOrGDS()
112 if (MI.getOperand(GDS).getImm()) in isSendMsgTraceDataOrGDS()
119 static bool isPermlane(const MachineInstr &MI) { in isPermlane() argument
120 unsigned Opcode = MI.getOpcode(); in isPermlane()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86ATTInstPrinter.h27 void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
29 bool printVecCompareInstr(const MCInst *MI, raw_ostream &OS);
33 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
34 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
38 void printInstruction(const MCInst *MI, uint64_t Address, raw_ostream &OS);
41 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS) override;
42 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
44 void printSrcIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
45 void printDstIdx(const MCInst *MI, unsigned Op, raw_ostream &O);
[all …]
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h57 unsigned isLoadFromStackSlot(const MachineInstr &MI,
65 unsigned isStoreToStackSlot(const MachineInstr &MI,
72 const MachineInstr &MI,
79 const MachineInstr &MI,
204 bool expandPostRAPseudo(MachineInstr &MI) const override;
220 MachineBasicBlock::iterator MI) const override;
223 bool isPredicated(const MachineInstr &MI) const override;
226 bool isPostIncrement(const MachineInstr &MI) const override;
230 bool PredicateInstruction(MachineInstr &MI,
241 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred,
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/external/llvm/lib/Target/SystemZ/
DSystemZShortenInst.cpp44 bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH);
45 bool shortenOn0(MachineInstr &MI, unsigned Opcode);
46 bool shortenOn01(MachineInstr &MI, unsigned Opcode);
47 bool shortenOn001(MachineInstr &MI, unsigned Opcode);
48 bool shortenOn001AddCC(MachineInstr &MI, unsigned Opcode);
49 bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
67 static void tieOpsIfNeeded(MachineInstr &MI) { in tieOpsIfNeeded() argument
68 if (MI.getDesc().getOperandConstraint(0, MCOI::TIED_TO) && in tieOpsIfNeeded()
69 !MI.getOperand(0).isTied()) in tieOpsIfNeeded()
70 MI.tieOperands(0, 1); in tieOpsIfNeeded()
[all …]

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