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Searched refs:MIB (Results 1 – 25 of 342) sorted by relevance

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/external/libcups/backend/
Dsnmp.txt14 SNMPv2-MIB::sysDescr.0 = STRING: HP ETHERNET MULTI-ENVIRONMENT,ROM J.sp.00,JETDIRECT EX,JD28,EEPROM…
15 SNMPv2-MIB::sysName.0 = STRING:
16 HOST-RESOURCES-MIB::hrDeviceType.1 = OID: HOST-RESOURCES-TYPES::hrDevicePrinter
17 HOST-RESOURCES-MIB::hrDeviceType.2 = OID: HOST-RESOURCES-TYPES::hrDevicePrinter
18 HOST-RESOURCES-MIB::hrDeviceType.3 = OID: HOST-RESOURCES-TYPES::hrDevicePrinter
19 HOST-RESOURCES-MIB::hrDeviceDescr.1 = STRING: Hewlett-Packard hp LaserJet 3380
20 HOST-RESOURCES-MIB::hrDeviceDescr.2 = STRING: Axis AXIS 5600
21 HOST-RESOURCES-MIB::hrDeviceDescr.3 = STRING: Axis AXIS 5600
22 HOST-RESOURCES-MIB::hrDeviceID.1 = OID: SNMPv2-SMI::zeroDotZero
23 HOST-RESOURCES-MIB::hrDeviceID.2 = OID: SNMPv2-SMI::zeroDotZero
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/external/llvm-project/llvm/lib/Target/ARM/
DMVETailPredUtils.h84 MachineInstrBuilder MIB = variable
86 MIB.add(MI->getOperand(0));
87 MIB.addImm(0);
88 MIB.addImm(ARMCC::AL);
89 MIB.addReg(ARM::NoRegister);
92 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc));
93 MIB.add(MI->getOperand(1)); // branch target
94 MIB.addImm(ARMCC::EQ); // condition code
95 MIB.addReg(ARM::CPSR);
114 MachineInstrBuilder MIB = variable
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DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
231 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
240 Register VReg0 = MIB.getReg(0); in selectMergeValues()
245 Register VReg1 = MIB.getReg(1); in selectMergeValues()
250 Register VReg2 = MIB.getReg(2); in selectMergeValues()
256 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
257 MIB.add(predOps(ARMCC::AL)); in selectMergeValues()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp47 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
60 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
62 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
233 static bool selectMergeValues(MachineInstrBuilder &MIB, in selectMergeValues() argument
242 Register VReg0 = MIB->getOperand(0).getReg(); in selectMergeValues()
247 Register VReg1 = MIB->getOperand(1).getReg(); in selectMergeValues()
252 Register VReg2 = MIB->getOperand(2).getReg(); in selectMergeValues()
258 MIB->setDesc(TII.get(ARM::VMOVDRR)); in selectMergeValues()
259 MIB.add(predOps(ARMCC::AL)); in selectMergeValues()
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DARMExpandPseudoInsts.cpp479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
512 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
515 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
516 MIB.add(MI.getOperand(OpIdx++)); in ExpandVLD()
540 MIB.add(AM6Offset); in ExpandVLD()
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DARMLowOverheadLoops.cpp687 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), in RevertWhile() local
689 MIB.add(MI->getOperand(0)); in RevertWhile()
690 MIB.addImm(0); in RevertWhile()
691 MIB.addImm(ARMCC::AL); in RevertWhile()
692 MIB.addReg(ARM::NoRegister); in RevertWhile()
698 MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(BrOpc)); in RevertWhile()
699 MIB.add(MI->getOperand(1)); // branch target in RevertWhile()
700 MIB.addImm(ARMCC::EQ); // condition code in RevertWhile()
701 MIB.addReg(ARM::CPSR); in RevertWhile()
716 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), in RevertLoopDec() local
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/external/llvm-project/llvm/lib/Target/X86/
DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrBuilder.h124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
143 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) { in addOffset() argument
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0); in addOffset()
157 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
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DX86CallLowering.cpp100 MachineInstrBuilder &MIB, CCAssignFn *AssignFn) in OutgoingValueHandler()
101 : ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB), in OutgoingValueHandler()
126 MIB.addUse(PhysReg, RegState::Implicit); in assignValueToReg()
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg); in assignValueToReg() local
142 ExtReg = MIB->getOperand(0).getReg(); in assignValueToReg()
178 MachineInstrBuilder &MIB; member
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0); in lowerReturn() local
218 OutgoingValueHandler Handler(MIRBuilder, MRI, MIB, RetCC_X86); in lowerReturn()
223 MIRBuilder.insertInstr(MIB); in lowerReturn()
314 CCAssignFn *AssignFn, MachineInstrBuilder &MIB) in CallReturnHandler()
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/external/llvm/lib/Target/X86/
DX86InstrBuilder.h119 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { in addDirectMem() argument
122 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0); in addDirectMem()
127 addOffset(const MachineInstrBuilder &MIB, int Offset) { in addOffset() argument
128 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0); in addOffset()
136 addRegOffset(const MachineInstrBuilder &MIB, in addRegOffset() argument
138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
143 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB, in addRegReg() argument
146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
151 addFullAddress(const MachineInstrBuilder &MIB, in addFullAddress() argument
156 MIB.addReg(AM.Base.Reg); in addFullAddress()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp190 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
223 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
236 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
248 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
303 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
345 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
347 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
348 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp193 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
231 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
244 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
256 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
299 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
311 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
353 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
355 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
356 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
363 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp208 MachineInstrBuilder &MIB, in CreateVirtualRegisters() argument
241 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
254 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
266 MIB.addReg(VRBase, RegState::Define); in CreateVirtualRegisters()
312 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, in AddRegisterOperand() argument
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
358 unsigned Idx = MIB->getNumOperands(); in AddRegisterOperand()
360 MIB->getOperand(Idx-1).isReg() && in AddRegisterOperand()
361 MIB->getOperand(Idx-1).isImplicit()) in AddRegisterOperand()
368 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) | in AddRegisterOperand()
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/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD() local
409 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
411 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
413 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
415 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); in ExpandVLD()
418 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
421 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
422 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
425 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
435 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DCSEMIRBuilder.cpp120 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
122 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
124 MachineInstr *MIBInstr = MIB; in memoizeMI()
126 return MIB; in memoizeMI()
141 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
147 return buildCopy(Op.getReg(), MIB.getReg(0)); in generateCopiesIfRequired()
157 Observer->changingInstr(*MIB); in generateCopiesIfRequired()
158 MIB->setDebugLoc( in generateCopiesIfRequired()
159 DILocation::getMergedLocation(MIB->getDebugLoc(), getDebugLoc())); in generateCopiesIfRequired()
161 Observer->changedInstr(*MIB); in generateCopiesIfRequired()
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DMachineIRBuilder.cpp41 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert() local
42 return MIB; in buildInstrNoInsert()
45 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
46 getMBB().insert(getInsertPt(), MIB); in insertInstr()
47 recordInsertion(MIB); in insertInstr()
48 return MIB; in insertInstr()
100 auto MIB = buildInstrNoInsert(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
103 MIB.addCImm(CI); in buildConstDbgValue()
105 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
107 MIB.addFPImm(CFP); in buildConstDbgValue()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DCSEMIRBuilder.cpp105 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB, in memoizeMI() argument
107 assert(canPerformCSEForOpc(MIB->getOpcode()) && in memoizeMI()
109 MachineInstr *MIBInstr = MIB; in memoizeMI()
111 return MIB; in memoizeMI()
126 MachineInstrBuilder &MIB) { in generateCopiesIfRequired() argument
132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg()); in generateCopiesIfRequired()
134 return MIB; in generateCopiesIfRequired()
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag); in buildInstr() local
186 getCSEInfo()->handleRemoveInst(&*MIB); in buildInstr()
187 return MIB; in buildInstr()
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DMachineIRBuilder.cpp79 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode)); in buildInstrNoInsert() local
80 return MIB; in buildInstrNoInsert()
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { in insertInstr() argument
84 getMBB().insert(getInsertPt(), MIB); in insertInstr()
85 recordInsertion(MIB); in insertInstr()
86 return MIB; in insertInstr()
138 auto MIB = buildInstr(TargetOpcode::DBG_VALUE); in buildConstDbgValue() local
141 MIB.addCImm(CI); in buildConstDbgValue()
143 MIB.addImm(CI->getZExtValue()); in buildConstDbgValue()
145 MIB.addFPImm(CFP); in buildConstDbgValue()
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp521 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
525 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
526 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
663 auto MIB = BuildMI(*BB, &MI, DL, TII.get(AMDGPU::S_LSHR_B32), Dst) in selectG_BUILD_VECTOR_TRUNC() local
668 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectG_BUILD_VECTOR_TRUNC()
815 auto MIB = BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::V_WRITELANE_B32), VDst); in selectWritelane() local
822 MIB.addReg(Val); in selectWritelane()
823 MIB.addImm(ConstSelect->Value & in selectWritelane()
833 MIB.addImm(ConstVal->Value); in selectWritelane()
834 MIB.addReg(LaneSelect); in selectWritelane()
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DAMDGPUInstructionSelector.h269 void renderTruncImm32(MachineInstrBuilder &MIB, const MachineInstr &MI,
272 void renderTruncTImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
275 void renderTruncTImm1(MachineInstrBuilder &MIB, const MachineInstr &MI, in renderTruncTImm1() argument
277 renderTruncTImm(MIB, MI, OpIdx); in renderTruncTImm1()
280 void renderTruncTImm8(MachineInstrBuilder &MIB, const MachineInstr &MI, in renderTruncTImm8() argument
282 renderTruncTImm(MIB, MI, OpIdx); in renderTruncTImm8()
285 void renderTruncTImm16(MachineInstrBuilder &MIB, const MachineInstr &MI, in renderTruncTImm16() argument
287 renderTruncTImm(MIB, MI, OpIdx); in renderTruncTImm16()
290 void renderTruncTImm32(MachineInstrBuilder &MIB, const MachineInstr &MI, in renderTruncTImm32() argument
292 renderTruncTImm(MIB, MI, OpIdx); in renderTruncTImm32()
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/external/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp313 MachineInstrBuilder MIB; in changeLoad() local
319 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
320 MIB.addOperand(OldMI->getOperand(0)); in changeLoad()
321 MIB.addOperand(OldMI->getOperand(2)); in changeLoad()
322 MIB.addOperand(OldMI->getOperand(3)); in changeLoad()
323 MIB.addOperand(ImmOp); in changeLoad()
329 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
334 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
341 DEBUG(dbgs() << "[TO]: " << MIB << "\n"); in changeLoad()
345 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp504 MachineInstrBuilder MIB = in selectG_MERGE_VALUES() local
508 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef())); in selectG_MERGE_VALUES()
509 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
1004 MachineInstrBuilder MIB = B.buildInstr(Opc) in selectStoreIntrinsic() local
1008 MIB.addUse(VOffset); in selectStoreIntrinsic()
1010 MIB.addUse(RSrc) in selectStoreIntrinsic()
1022 return constrainSelectedInstRegOperands(*MIB, TII, TRI, RBI); in selectStoreIntrinsic()
1868 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVCSRC()
1899 [=](MachineInstrBuilder &MIB) { MIB.add(Root); } in selectVSRC0()
1910 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); }, in selectVOP3Mods0()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp492 MachineInstrBuilder MIB; in changeLoad() local
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
499 MIB.add(OldMI->getOperand(0)); in changeLoad()
500 MIB.add(OldMI->getOperand(2)); in changeLoad()
501 MIB.add(OldMI->getOperand(3)); in changeLoad()
502 MIB.add(ImmOp); in changeLoad()
509 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
521 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
526 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonOptAddrMode.cpp492 MachineInstrBuilder MIB; in changeLoad() local
498 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
499 MIB.add(OldMI->getOperand(0)); in changeLoad()
500 MIB.add(OldMI->getOperand(2)); in changeLoad()
501 MIB.add(OldMI->getOperand(3)); in changeLoad()
502 MIB.add(ImmOp); in changeLoad()
509 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)) in changeLoad()
514 MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags()); in changeLoad()
521 LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n"); in changeLoad()
526 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode)); in changeLoad()
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/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp108 MachineIRBuilder &MIB) const;
110 MachineIRBuilder &MIB) const;
112 MachineIRBuilder &MIB) const;
115 MachineIRBuilder &MIB) const;
274 MachineIRBuilder &MIB) const;
279 MachineIRBuilder &MIB) const;
382 MachineIRBuilder &MIB) const;
386 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI,
388 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I,
390 void renderLogicalImm64(MachineInstrBuilder &MIB, const MachineInstr &I,
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12345678910>>...14