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Searched refs:MIDR (Results 1 – 10 of 10) sorted by relevance

/external/arm-trusted-firmware/lib/cpus/aarch32/
Dcpu_helpers.S129 ldcopr r2, MIDR
159 ldcopr r1, MIDR
/external/arm-trusted-firmware/include/lib/cpus/aarch32/
Dcpu_macros.S223 ldcopr r0, MIDR
/external/arm-trusted-firmware/docs/
Dchange-log-upcoming.rst104 - Example: "cortex-a12: Fix MIDR mask"
Dchange-log.rst1431 - cortex-a12: Fix MIDR mask
/external/XNNPACK/third_party/
Dcpuinfo.patch116 * Use a MIDR-based heuristic to whitelist processors known to support it:
200 * Use a MIDR-based heuristic to whitelist processors known to support it:
266 * Use a MIDR-based heuristic to whitelist processors known to support it.
/external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/
Ddevice1.ini30 MIDR=0x412FC0F1 key
/external/arm-trusted-firmware/include/arch/aarch32/
Darch_helpers.h218 DEFINE_COPROCR_READ_FUNC(midr, MIDR) in DEFINE_SYSREG_RW_FUNCS()
Darch.h501 #define MIDR p15, 0, c0, c0, 0 macro
/external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/
Ddevice1.ini30 MIDR=0x412FC0F1 key
/external/cpuinfo/
DREADME.md22 - ID (**MIDR** on ARM, **CPUID** leaf 1 EAX value on x86) for each CPU core