Searched refs:MIDR_PN_MASK (Results 1 – 11 of 11) sorted by relevance
17 (MIDR_PN_MASK << MIDR_PN_SHIFT)225 ldr r1, =((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
14 (MIDR_PN_MASK << MIDR_PN_SHIFT)302 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
26 (MIDR_PN_MASK << MIDR_PN_SHIFT); in midr_match()
34 cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
37 cmp w0, #((CORTEX_A72_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
349 cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
65 mov x1, #(MIDR_PN_MASK << MIDR_PN_SHIFT)
625 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
743 midr = reg & (MIDR_PN_MASK << MIDR_PN_SHIFT); in bl2_el3_early_platform_setup()
21 #define MIDR_PN_MASK U(0xfff) macro
24 #define MIDR_PN_MASK U(0xfff) macro