| /external/mesa3d/src/amd/compiler/ |
| D | aco_opcodes.py | 44 MIMG = 11 variable in Format
100 elif self == Format.MIMG:
1372 opcode(name, code, code, code, Format.MIMG)
1374 opcode("image_msaa_load", -1, -1, 0x80, Format.MIMG) #GFX10.3+
1398 opcode(name, gfx7, gfx89, gfx7, Format.MIMG, is_atomic = True)
1444 opcode(name, code, code, code, Format.MIMG)
1477 opcode(name, code, code, code, Format.MIMG)
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| D | aco_insert_waitcnt.cpp | 418 …bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->op… in check_instr()
816 case Format::MIMG: in gen()
821 …bool has_sampler = instr->format == Format::MIMG && !instr->operands[1].isUndefined() && instr->op… in gen()
827 instr->format != Format::MIMG && in gen()
833 instr->format == Format::MIMG && in gen()
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| D | aco_opt_value_numbering.cpp | 107 case Format::MIMG: in operator ()()
308 case Format::MIMG: { in operator ()()
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| D | aco_ir.cpp | 144 case Format::MIMG: in get_sync_info()
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| D | README-ISA.md | 76 ## MIMG opcodes on GFX8/GCN3
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| D | aco_validate.cpp | 214 (flat && i == 1) || (instr->format == Format::MIMG && i == 1) || in validate_ir()
437 case Format::MIMG: { in validate_ir()
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| D | aco_ir.h | 85 MIMG = 11, enumerator
939 format == Format::MIMG; in isVMEM()
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| D | aco_print_ir.cpp | 389 case Format::MIMG: { in print_instr_format_specific()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 1 //===-- MIMGInstructions.td - MIMG Instruction Defintions -----------------===//
9 // MIMG-specific encoding families to distinguish between semantically
125 let MIMG = 1;
138 class MIMG <dag outs, string dns = "">
152 let FilterClass = "MIMG";
182 // Base class of all pre-gfx10 MIMG instructions.
184 : MIMG<outs, dns>, MIMGe_gfx6789<op> {
193 // Base class of all non-NSA gfx10 MIMG instructions.
195 : MIMG<outs, dns>, MIMGe_gfx10<op> {
205 // Base class for all NSA MIMG instructions. Note that 1-dword addresses always
[all …]
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| D | SILoadStoreOptimizer.cpp | 101 MIMG, enumerator
336 return MIMG; in getInstClass()
496 if (InstClass == MIMG) { in setMI()
510 } else if (InstClass != MIMG) { in setMI()
662 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
724 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
915 CI.InstClass == MIMG in findMatchingInst()
1439 case MIMG: in getNewOpcode()
1452 if (CI.InstClass == MIMG) { in getSubRegIdxs()
2025 case MIMG: { in optimizeInstsWithSameBaseAddr()
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| D | SIInstrFormats.td | 41 field bit MIMG = 0;
153 let TSFlags{19} = MIMG;
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| D | SIDefines.h | 48 MIMG = 1 << 19, enumerator
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| D | SIInstrInfo.h | 482 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
486 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1105 // MIMG Instructions
2524 class SampleRawPattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2533 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2534 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
2535 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V4), v4i32>;
2536 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V8), v8i32>;
2537 def : SampleRawPattern<name, !cast<MIMG>(opcode # _V4_V16), v16i32>;
2541 class ImagePattern<SDPatternOperator name, MIMG opcode, ValueType vt> : Pat <
2550 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V1), i32>;
2551 def : ImagePattern<name, !cast<MIMG>(opcode # _V4_V2), v2i32>;
[all …]
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| D | SIInstrFormats.td | 42 field bits<1> MIMG = 0;
78 let TSFlags{20} = MIMG;
729 class MIMG <dag outs, dag ins, string asm, list<dag> pattern> :
734 let MIMG = 1;
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| D | SIDefines.h | 39 MIMG = 1 << 20, enumerator
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| D | SIInstrInfo.h | 312 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
316 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | MIMGInstructions.td | 1 //===-- MIMGInstructions.td - MIMG Instruction Definitions ----------------===//
9 // MIMG-specific encoding families to distinguish between semantically
142 let MIMG = 1;
154 class MIMG <dag outs, string dns = "">
168 let FilterClass = "MIMG";
198 // Base class of all pre-gfx10 MIMG instructions.
200 : MIMG<outs, dns>, MIMGe_gfx6789<op> {
209 // Base class of all non-NSA gfx10 MIMG instructions.
211 : MIMG<outs, dns>, MIMGe_gfx10<op> {
221 // Base class for all NSA MIMG instructions. Note that 1-dword addresses always
[all …]
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| D | SILoadStoreOptimizer.cpp | 101 MIMG, enumerator
363 return MIMG; in getInstClass()
529 if (InstClass == MIMG) { in setMI()
545 } else if (InstClass != MIMG) { in setMI()
690 assert(CI.InstClass == MIMG); in dmasksCanBeCombined()
754 assert(CI.InstClass != MIMG); in offsetsCanBeCombined()
873 if (CI.InstClass == MIMG && !dmasksCanBeCombined(CI, *TII, Paired)) in checkAndPrepareMerge()
876 if (CI.InstClass != MIMG && in checkAndPrepareMerge()
975 if (CI.InstClass != MIMG) in checkAndPrepareMerge()
1502 case MIMG: in getNewOpcode()
[all …]
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| D | SIPostRABundler.cpp | 95 SIInstrFlags::FLAT | SIInstrFlags::MIMG; in runOnMachineFunction()
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| D | SIInstrFormats.td | 42 field bit MIMG = 0;
162 let TSFlags{20} = MIMG;
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| D | SIDefines.h | 49 MIMG = 1 << 20, enumerator
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| D | SIInstrInfo.h | 488 return MI.getDesc().TSFlags & SIInstrFlags::MIMG; in isMIMG()
492 return get(Opcode).TSFlags & SIInstrFlags::MIMG; in isMIMG()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 294 if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 306 if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) { in encodeInstruction()
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