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Searched refs:MI_FLUSH (Results 1 – 11 of 11) sorted by relevance

/external/libdrm/intel/tests/
Dgen5-3d.batch-ref.txt32 0x1230007c: 0x02000000: MI_FLUSH
71 0x12300118: 0x02000000: MI_FLUSH
97 0x12300180: 0x02000000: MI_FLUSH
116 0x123001cc: 0x02000000: MI_FLUSH
135 0x12300218: 0x02000000: MI_FLUSH
156 0x1230026c: 0x02000000: MI_FLUSH
169 0x123002a0: 0x02000000: MI_FLUSH
198 0x12300314: 0x02000000: MI_FLUSH
220 0x1230036c: 0x02000000: MI_FLUSH
247 0x123003d8: 0x02000000: MI_FLUSH
[all …]
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h36 #define MI_FLUSH (CMD_MI | (4 << 23)) macro
Dintel_batchbuffer.c263 OUT_BATCH(MI_FLUSH); in intel_batchbuffer_emit_mi_flush()
Di915_vtbl.c658 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE; in i915_set_draw_region()
/external/mesa3d/src/gallium/drivers/i915/
Di915_state_emit.c68 OUT_BATCH(MI_FLUSH | FLUSH_MAP_CACHE); in emit_flush()
70 OUT_BATCH(MI_FLUSH | INHIBIT_FLUSH_RENDER_CACHE); in emit_flush()
Di915_reg.h861 #define MI_FLUSH ((0<<29)|(4<<23)) macro
/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_misc_state.c62 OUT_BATCH(MI_FLUSH); in upload_pipelined_state_pointers()
553 OUT_BATCH(MI_FLUSH); in brw_emit_select_pipeline()
Dbrw_defines.h1429 #define MI_FLUSH (CMD_MI | (4 << 23)) macro
/external/igt-gpu-tools/lib/
Di830_reg.h34 #define MI_FLUSH (0x04<<23) macro
Drendercopy_gen4.c323 OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); in gen4_emit_invariant()
Dintel_reg.h2575 #define MI_FLUSH (0x04<<23) macro