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Searched refs:MI_PREDICATE_SRC0 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_conditional_render.c68 brw_load_register_reg64(brw, MI_PREDICATE_SRC0, HSW_CS_GPR(0)); in set_predicate_for_overflow_query()
89 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query->bo, 0 /* offset */); in set_predicate_for_occlusion_query()
Dhsw_queryobj.c390 brw_load_register_mem64(brw, MI_PREDICATE_SRC0, query_bo, in set_predicate()
Dbrw_draw.c1201 brw_load_register_mem(brw, MI_PREDICATE_SRC0, in brw_draw_prims()
1205 brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0); in brw_draw_prims()
Dbrw_defines.h1585 #define MI_PREDICATE_SRC0 0x2400 macro
DgenX_state_upload.c4429 #define MI_PREDICATE_SRC0 0x2400 macro
4444 emit_lri(brw, MI_PREDICATE_SRC0 + 4, 0);
4449 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 0));
4459 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 4));
4469 emit_lrm(brw, MI_PREDICATE_SRC0, ro_bo(bo, indirect_offset + 8));
/external/mesa3d/src/gallium/drivers/iris/
Diris_defines.h46 #define MI_PREDICATE_SRC0 0x2400 macro
Diris_state.c6559 iris_load_register_mem32(batch, MI_PREDICATE_SRC0, in iris_upload_render_state()
6562 iris_load_register_imm32(batch, MI_PREDICATE_SRC0 + 4, 0); in iris_upload_render_state()
/external/mesa3d/src/intel/vulkan/
DgenX_cmd_buffer.c720 #define MI_PREDICATE_SRC0 0x2400 macro
800 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), in anv_cmd_compute_resolve_predicate()
812 gen_mi_inot(&b, gen_mi_reg64(MI_PREDICATE_SRC0))); in anv_cmd_compute_resolve_predicate()
826 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), in anv_cmd_compute_resolve_predicate()
887 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), fast_clear_type_mem); in anv_cmd_simple_resolve_predicate()
4089 gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0), in prepare_for_draw_count_predicate()
4146 gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0), pred); in emit_draw_count_predicate_with_conditional_render()
4658 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC0), size_x); in genX()
4667 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_y); in genX()
4675 gen_mi_store(&b, gen_mi_reg32(MI_PREDICATE_SRC0), size_z); in genX()
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DgenX_query.c1167 #define MI_PREDICATE_SRC0 0x2400 macro
1185 gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC0), gen_mi_mem64(poll_addr)); in gpu_write_query_result_cond()