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Searched refs:MI_PREDICATE_SRC1 (Results 1 – 9 of 9) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_conditional_render.c69 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull); in set_predicate_for_overflow_query()
90 brw_load_register_mem64(brw, MI_PREDICATE_SRC1, query->bo, 8 /* offset */); in set_predicate_for_occlusion_query()
Dhsw_queryobj.c387 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, 0ull); in set_predicate()
Dbrw_defines.h1586 #define MI_PREDICATE_SRC1 0x2408 macro
Dbrw_draw.c1207 brw_load_register_imm64(brw, MI_PREDICATE_SRC1, prims[i].draw_id); in brw_draw_prims()
DgenX_state_upload.c4430 #define MI_PREDICATE_SRC1 0x2408 macro
4445 emit_lri(brw, MI_PREDICATE_SRC1 , 0);
4446 emit_lri(brw, MI_PREDICATE_SRC1 + 4, 0);
/external/mesa3d/src/gallium/drivers/iris/
Diris_defines.h47 #define MI_PREDICATE_SRC1 0x2408 macro
Diris_state.c6555 iris_load_register_imm64(batch, MI_PREDICATE_SRC1, draw->drawid); in iris_upload_render_state()
/external/mesa3d/src/intel/vulkan/
DgenX_query.c1168 #define MI_PREDICATE_SRC1 0x2408 macro
1186 gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(ref_value)); in gpu_write_query_result_cond()
DgenX_cmd_buffer.c721 #define MI_PREDICATE_SRC1 0x2408 macro
846 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0)); in anv_cmd_compute_resolve_predicate()
888 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0)); in anv_cmd_simple_resolve_predicate()
4092 gen_mi_store(b, gen_mi_reg32(MI_PREDICATE_SRC1 + 4), gen_mi_imm(0)); in prepare_for_draw_count_predicate()
4104 gen_mi_store(b, gen_mi_reg32(MI_PREDICATE_SRC1), gen_mi_imm(draw_index)); in emit_draw_count_predicate()
4147 gen_mi_store(b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0)); in emit_draw_count_predicate_with_conditional_render()
4659 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0)); in genX()
6097 gen_mi_store(&b, gen_mi_reg64(MI_PREDICATE_SRC1), gen_mi_imm(0)); in genX()