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Searched refs:MIb (Results 1 – 25 of 55) sorted by relevance

123

/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp352 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
356 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
571 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
576 Pair.second.insert(MIb); in runOnMachineFunction()
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
600 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
601 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
610 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
614 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
615 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
/external/llvm-project/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp351 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
355 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
570 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
575 Pair.second.insert(MIb); in runOnMachineFunction()
595 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
599 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
600 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
609 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
613 LLVM_DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
614 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ControlFlowFinalizer.cpp337 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), in MakeFetchClause() local
341 return ClauseFile(MIb, std::move(ClauseContent)); in MakeFetchClause()
557 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
562 Pair.second.insert(MIb); in runOnMachineFunction()
582 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
586 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
587 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
596 MachineInstr *MIb = BuildMI(MBB, MI, MBB.findDebugLoc(MI), in runOnMachineFunction() local
600 DEBUG(dbgs() << CfCount << ":"; MIb->dump();); in runOnMachineFunction()
601 IfThenElseStack.push_back(MIb); in runOnMachineFunction()
[all …]
DSIInstrInfo.cpp1342 MachineInstr &MIb) const { in checkInstOffsetsDoNotOverlap()
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
1349 if (!MIa.hasOneMemOperand() || !MIb.hasOneMemOperand()) { in checkInstOffsetsDoNotOverlap()
1354 unsigned Width1 = (*MIb.memoperands_begin())->getSize(); in checkInstOffsetsDoNotOverlap()
1365 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
1369 assert((MIb.mayLoad() || MIb.mayStore()) && in areMemAccessesTriviallyDisjoint()
1372 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects()) in areMemAccessesTriviallyDisjoint()
1376 if (MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
1385 if (isDS(MIb)) in areMemAccessesTriviallyDisjoint()
1386 return checkInstOffsetsDoNotOverlap(MIa, MIb); in areMemAccessesTriviallyDisjoint()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp580 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
588 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
593 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
602 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
616 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
628 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
634 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
635 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
637 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
638 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
[all …]
DHexagonMCCompound.cpp335 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
337 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
345 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCInstrInfo.h224 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
259 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp573 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
580 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
585 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
594 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
608 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
620 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
626 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
627 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
629 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
630 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
[all …]
DHexagonMCCompound.cpp346 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
348 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
356 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCInstrInfo.h201 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
238 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp578 MCInst const &MIb, bool ExtendedB, in isOrderedDuplexPair() argument
586 unsigned Opcode = MIb.getOpcode(); in isOrderedDuplexPair()
591 MIbG = HexagonMCInstrInfo::getDuplexCandidateGroup(MIb); in isOrderedDuplexPair()
600 MCInst SubInst1 = HexagonMCInstrInfo::deriveSubInst(MIb); in isOrderedDuplexPair()
614 if (MIb.getOpcode() == Hexagon::S2_allocframe) in isOrderedDuplexPair()
626 if (subInstWouldBeExtended(MIb) && !ExtendedB) in isOrderedDuplexPair()
632 if ((MIb.getNumOperands() > 1) && MIb.getOperand(1).isReg() && in isOrderedDuplexPair()
633 (MIb.getOperand(1).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
635 if ((MIb.getNumOperands() > 0) && MIb.getOperand(0).isReg() && in isOrderedDuplexPair()
636 (MIb.getOperand(0).getReg() == Hexagon::R31)) in isOrderedDuplexPair()
[all …]
DHexagonMCCompound.cpp336 MCInst const &MIb, bool IsExtendedB) { in isOrderedCompoundPair() argument
338 unsigned MIbG = getCompoundCandidateGroup(MIb, IsExtendedB); in isOrderedCompoundPair()
346 (MIa.getOperand(0).getReg() == MIb.getOperand(0).getReg())); in isOrderedCompoundPair()
DHexagonMCInstrInfo.h231 bool isDuplexPair(MCInst const &MIa, MCInst const &MIb);
268 bool ExtendedA, MCInst const &MIb, bool ExtendedB,
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp90 MachineInstr &MIb, in areMemAccessesTriviallyDisjoint() argument
93 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
95 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
96 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
109 getMemOpBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h38 bool areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h39 const MachineInstr &MIb) const override;
/external/llvm-project/llvm/lib/Target/Lanai/
DLanaiInstrInfo.cpp89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
91 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
93 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
94 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
107 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DLanaiInstrInfo.h39 const MachineInstr &MIb) const override;
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp586 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
588 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
590 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
591 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
604 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DRISCVInstrInfo.h95 const MachineInstr &MIb) const override;
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp654 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint()
656 assert(MIb.mayLoadOrStore() && "MIb must be a load or store."); in areMemAccessesTriviallyDisjoint()
658 if (MIa.hasUnmodeledSideEffects() || MIb.hasUnmodeledSideEffects() || in areMemAccessesTriviallyDisjoint()
659 MIa.hasOrderedMemoryRef() || MIb.hasOrderedMemoryRef()) in areMemAccessesTriviallyDisjoint()
672 getMemOperandWithOffsetWidth(MIb, BaseOpB, OffsetB, WidthB, TRI)) { in areMemAccessesTriviallyDisjoint()
DRISCVInstrInfo.h98 const MachineInstr &MIb) const override;
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.h269 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
302 bool isDuplexPair(const MachineInstr *MIa, const MachineInstr *MIb) const;
/external/llvm/include/llvm/Target/
DTargetInstrInfo.h1427 areMemAccessesTriviallyDisjoint(MachineInstr &MIa, MachineInstr &MIb,
1431 assert((MIb.mayLoad() || MIb.mayStore()) &&

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