| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 742 MLOAD, MSTORE, enumerator
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| D | SelectionDAGNodes.h | 1115 N->getOpcode() == ISD::MLOAD ||
1882 return N->getOpcode() == ISD::MLOAD ||
1893 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, MemVT, MMO) {
1902 return N->getOpcode() == ISD::MLOAD;
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | SelectionDAGNodes.h | 1416 N->getOpcode() == ISD::MLOAD ||
2299 return getOperand(getOpcode() == ISD::MLOAD ? 1 : 2);
2302 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2305 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2321 return N->getOpcode() == ISD::MLOAD ||
2334 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2349 return N->getOpcode() == ISD::MLOAD;
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| D | ISDOpcodes.h | 892 MLOAD, MSTORE, enumerator
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| /external/capstone/arch/EVM/ |
| D | EVMMappingInsn.inc | 85 { 1, 1, 3 }, // MLOAD
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 1077 MLOAD, enumerator
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| D | SelectionDAGNodes.h | 1376 N->getOpcode() == ISD::MLOAD ||
2314 return getOperand(getOpcode() == ISD::MLOAD ? 2 : 3);
2317 return getOperand(getOpcode() == ISD::MLOAD ? 3 : 4);
2333 return N->getOpcode() == ISD::MLOAD ||
2346 : MaskedLoadStoreSDNode(ISD::MLOAD, Order, dl, VTs, AM, MemVT, MMO) {
2361 return N->getOpcode() == ISD::MLOAD;
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLoweringHVX.cpp | 114 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
169 setOperationAction(ISD::MLOAD, T, Custom); in initializeHVXLowering()
217 setOperationAction(ISD::MLOAD, BoolW, Custom); in initializeHVXLowering()
1699 assert(Opc == ISD::MLOAD || Opc == ISD::MSTORE); in LowerHvxMaskedOp()
1701 if (Opc == ISD::MLOAD) { in LowerHvxMaskedOp()
1831 assert(MemOpc == ISD::MLOAD || MemOpc == ISD::MSTORE); in SplitHvxMemOp()
1838 if (MemOpc == ISD::MLOAD) { in SplitHvxMemOp()
2031 case ISD::MLOAD: in LowerHvxOperation()
2084 case ISD::MLOAD: in LowerHvxOperation()
2121 case ISD::MLOAD: in LowerHvxOperationWrapper()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 294 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 608 case ISD::MLOAD: in SplitVectorResult()
2076 case ISD::MLOAD: in WidenVectorResult()
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| D | LegalizeIntegerTypes.cpp | 70 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
906 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 370 case ISD::MLOAD: return "masked_load"; in getOperationName()
|
| D | LegalizeIntegerTypes.cpp | 71 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1277 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| D | LegalizeVectorTypes.cpp | 843 case ISD::MLOAD: in SplitVectorResult()
2704 case ISD::MLOAD: in WidenVectorResult()
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| D | SelectionDAG.cpp | 576 case ISD::MLOAD: { in AddNodeIDCustom()
7081 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 382 case ISD::MLOAD: return "masked_load"; in getOperationName()
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| D | LegalizeVectorTypes.cpp | 902 case ISD::MLOAD: in SplitVectorResult()
2861 case ISD::MLOAD: in WidenVectorResult()
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| D | LegalizeIntegerTypes.cpp | 72 case ISD::MLOAD: Res = PromoteIntRes_MLOAD(cast<MaskedLoadSDNode>(N)); in PromoteIntegerResult()
1477 case ISD::MLOAD: Res = PromoteIntOp_MLOAD(cast<MaskedLoadSDNode>(N), in PromoteIntegerOperand()
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| D | SelectionDAG.cpp | 627 case ISD::MLOAD: { in AddNodeIDCustom()
7215 AddNodeIDNode(ID, ISD::MLOAD, VTs, Ops); in getMaskedLoad()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 527 def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1387 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
3472 case ISD::MLOAD: in Select()
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1434 case ISD::MLOAD: in SelectT2AddrModeImm7Offset()
3678 case ISD::MLOAD: in Select()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 622 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
|
| /external/llvm-project/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 631 def masked_ld : SDNode<"ISD::MLOAD", SDTMaskedLoad,
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 1091 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1211 setOperationAction(ISD::MLOAD, MVT::v8i32, Custom); in X86TargetLowering()
1212 setOperationAction(ISD::MLOAD, MVT::v8f32, Custom); in X86TargetLowering()
1402 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1488 setOperationAction(ISD::MLOAD, VT, Action); in X86TargetLowering()
1503 setOperationAction(ISD::MLOAD, VT, Legal); in X86TargetLowering()
1651 setTargetDAGCombine(ISD::MLOAD); in X86TargetLowering()
21763 case ISD::MLOAD: return LowerMLOAD(Op, Subtarget, DAG); in LowerOperation()
30967 case ISD::MLOAD: return combineMaskedLoad(N, DAG, DCI, Subtarget); in PerformDAGCombine()
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