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Searched refs:MO1 (Results 1 – 25 of 52) sorted by relevance

123

/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp81 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
92 printRegName(O, MO1.getReg()); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
114 printRegName(O, MO1.getReg()); in printInst()
315 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
316 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
317 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand()
323 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
345 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local
349 printRegName(O, MO1.getReg()); in printSORegRegOperand()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp101 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
112 printRegName(O, MO1.getReg()); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
134 printRegName(O, MO1.getReg()); in printInst()
354 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
355 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
356 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
384 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local
388 printRegName(O, MO1.getReg()); in printSORegRegOperand()
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DARMMCCodeEmitter.cpp601 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local
605 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
936 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local
938 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
1187 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local
1189 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue()
1254 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getLdStSORegOpValue() local
1257 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue()
1291 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode2OffsetOpValue() local
1292 unsigned Imm = MO1.getImm(); in getAddrMode2OffsetOpValue()
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/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
DARMInstPrinter.cpp101 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
112 printRegName(O, MO1.getReg()); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst() local
134 printRegName(O, MO1.getReg()); in printInst()
354 const MCOperand &MO1 = MI->getOperand(OpNum); in printThumbLdrLabelOperand() local
355 if (MO1.isExpr()) { in printThumbLdrLabelOperand()
356 MO1.getExpr()->print(O, &MAI); in printThumbLdrLabelOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
384 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand() local
388 printRegName(O, MO1.getReg()); in printSORegRegOperand()
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DARMMCCodeEmitter.cpp593 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local
597 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
928 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local
930 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
1179 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local
1181 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue()
1246 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getLdStSORegOpValue() local
1249 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue()
1283 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode2OffsetOpValue() local
1284 unsigned Imm = MO1.getImm(); in getAddrMode2OffsetOpValue()
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/external/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp55 static inline bool isIdenticalOp(const MachineOperand &MO1,
60 static bool isSimilarDispOp(const MachineOperand &MO1,
181 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument
183 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
184 (!MO1.isReg() || in isIdenticalOp()
185 !TargetRegisterInfo::isPhysicalRegister(MO1.getReg())); in isIdenticalOp()
195 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument
197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
199 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp67 static inline bool isIdenticalOp(const MachineOperand &MO1,
72 static bool isSimilarDispOp(const MachineOperand &MO1,
201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
204 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg())); in isIdenticalOp()
214 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86OptimizeLEAs.cpp67 static inline bool isIdenticalOp(const MachineOperand &MO1,
72 static bool isSimilarDispOp(const MachineOperand &MO1,
201 static inline bool isIdenticalOp(const MachineOperand &MO1, in isIdenticalOp() argument
203 return MO1.isIdenticalTo(MO2) && in isIdenticalOp()
204 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg())); in isIdenticalOp()
214 static bool isSimilarDispOp(const MachineOperand &MO1, in isSimilarDispOp() argument
216 assert(isValidDispOp(MO1) && isValidDispOp(MO2) && in isSimilarDispOp()
218 return (MO1.isImm() && MO2.isImm()) || in isSimilarDispOp()
219 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
220 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) || in isSimilarDispOp()
[all …]
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp555 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues() local
559 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
863 const MCOperand &MO1 = MI.getOperand(OpIdx); in getThumbAddrModeRegRegOpValue() local
865 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
1003 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getT2AddrModeImm0_1020s4OpValue() local
1005 unsigned Imm8 = MO1.getImm(); in getT2AddrModeImm0_1020s4OpValue()
1070 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getLdStSORegOpValue() local
1073 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue()
1107 const MCOperand &MO1 = MI.getOperand(OpIdx+1); in getAddrMode2OffsetOpValue() local
1108 unsigned Imm = MO1.getImm(); in getAddrMode2OffsetOpValue()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp483 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
484 unsigned Flags = MO1.getTargetFlags(); in expandMI()
491 if (MO1.isGlobal()) { in expandMI()
492 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags); in expandMI()
493 } else if (MO1.isSymbol()) { in expandMI()
494 MIB.addExternalSymbol(MO1.getSymbolName(), Flags); in expandMI()
496 assert(MO1.isCPI() && in expandMI()
498 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI()
523 if (MO1.isGlobal()) { in expandMI()
524 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI()
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/external/capstone/arch/ARM/
DARMInstPrinter.c477 MCOperand *MO1 = MCInst_getOperand(MI, 1); in ARM_printInst() local
515 printRegName(MI->csh, O, MCOperand_getReg(MO1)); in ARM_printInst()
519 …->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); in ARM_printInst()
540 MCOperand *MO1 = MCInst_getOperand(MI, 1); in ARM_printInst() local
577 printRegName(MI->csh, O, MCOperand_getReg(MO1)); in ARM_printInst()
580 …->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MO1); in ARM_printInst()
909 MCOperand *MO1 = MCInst_getOperand(MI, OpNum); in printThumbLdrLabelOperand() local
914 OffImm = (int32_t)MCOperand_getImm(MO1); in printThumbLdrLabelOperand()
946 MCOperand *MO1 = MCInst_getOperand(MI, OpNum); in printSORegRegOperand() local
951 printRegName(MI->csh, O, MCOperand_getReg(MO1)); in printSORegRegOperand()
[all …]
/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp774 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
775 unsigned Flags = MO1.getTargetFlags(); in expandMI()
782 if (MO1.isGlobal()) { in expandMI()
783 MIB.addGlobalAddress(MO1.getGlobal(), 0, Flags); in expandMI()
784 } else if (MO1.isSymbol()) { in expandMI()
785 MIB.addExternalSymbol(MO1.getSymbolName(), Flags); in expandMI()
787 assert(MO1.isCPI() && in expandMI()
789 MIB.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), Flags); in expandMI()
814 if (MO1.isGlobal()) { in expandMI()
815 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI()
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/external/llvm/lib/Target/AArch64/
DAArch64ExpandPseudoInsts.cpp837 const MachineOperand &MO1 = MI.getOperand(1); in expandMI() local
838 unsigned Flags = MO1.getTargetFlags(); in expandMI()
846 if (MO1.isGlobal()) { in expandMI()
847 MIB1.addGlobalAddress(MO1.getGlobal(), 0, Flags | AArch64II::MO_PAGE); in expandMI()
848 MIB2.addGlobalAddress(MO1.getGlobal(), 0, in expandMI()
850 } else if (MO1.isSymbol()) { in expandMI()
851 MIB1.addExternalSymbol(MO1.getSymbolName(), Flags | AArch64II::MO_PAGE); in expandMI()
852 MIB2.addExternalSymbol(MO1.getSymbolName(), in expandMI()
855 assert(MO1.isCPI() && in expandMI()
857 MIB1.addConstantPoolIndex(MO1.getIndex(), MO1.getOffset(), in expandMI()
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/external/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp123 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local
124 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/MCTargetDesc/
DMSP430MCCodeEmitter.cpp123 const MCOperand &MO1 = MI.getOperand(Op); in getMemOpValue() local
124 assert(MO1.isReg() && "Register operand expected"); in getMemOpValue()
125 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
/external/llvm-project/llvm/unittests/CodeGen/
DMachineOperandTest.cpp404 MachineOperand MO1 = MachineOperand::CreateES(SymName1); in TEST() local
407 ASSERT_EQ(hash_value(MO1), hash_value(MO2)); in TEST()
408 ASSERT_TRUE(MO1.isIdenticalTo(MO2)); in TEST()
/external/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp249 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
250 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
252 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
/external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
DAArch64MCCodeEmitter.cpp264 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in getAddSubImmOpValue() local
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
/external/llvm-project/llvm/lib/CodeGen/
DRegAllocFast.cpp1150 const MachineOperand &MO1 = MI.getOperand(I1); in allocateInstruction() local
1152 Register Reg1 = MO1.getReg(); in allocateInstruction()
1171 bool Livethrough1 = MO1.isEarlyClobber() || MO1.isTied() || in allocateInstruction()
1172 (MO1.getSubReg() == 0 && !MO1.isUndef()); in allocateInstruction()
/external/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp412 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
413 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg); in HexagonProcessInstruction()
414 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg); in HexagonProcessInstruction()
/external/llvm/lib/Target/AArch64/InstPrinter/
DAArch64InstPrinter.cpp1178 const MCOperand MO1 = MI->getOperand(OpNum + 1); in printAMIndexedWB() local
1180 if (MO1.isImm()) { in printAMIndexedWB()
1181 O << ", #" << formatImm(MO1.getImm() * Scale); in printAMIndexedWB()
1183 assert(MO1.isExpr() && "Unexpected operand type!"); in printAMIndexedWB()
1185 MO1.getExpr()->print(O, &MAI); in printAMIndexedWB()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp462 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonAsmPrinter.cpp462 MCOperand &MO1 = MappedInst.getOperand(1); in HexagonProcessInstruction() local
463 unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::isub_hi); in HexagonProcessInstruction()
464 unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::isub_lo); in HexagonProcessInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1223 static MCInst makeCombineInst(int opCode, MCOperand &Rdd, MCOperand &MO1, in makeCombineInst() argument
1228 TmpInst.addOperand(MO1); in makeCombineInst()
1584 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1592 Inst = makeCombineInst(Hexagon::A2_combineii, Rdd, MO1, MO2); in processInstruction()
1599 MCOperand &MO1 = Inst.getOperand(1); in processInstruction() local
1601 if (MO1.getExpr()->evaluateAsAbsolute(Value)) { in processInstruction()
1607 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, MO1, MO2); in processInstruction()

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