Searched refs:MPIDR_AFFLVL0_VAL (Results 1 – 21 of 21) sorted by relevance
44 core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on()61 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off()106 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend()128 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend_finish()
70 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on()103 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off()114 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend()167 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend_finish()
93 thread_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()98 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
38 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on()57 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_on_finish()83 cpu = MPIDR_AFFLVL0_VAL(mpidr); in hikey_pwr_domain_off()
51 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_off()87 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in sunxi_cpu_on()
24 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
46 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend()72 unsigned int core_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend_finish()
78 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_on()118 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_pwr_domain_off()137 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend()213 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in imx_domain_suspend_finish()
305 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_on()329 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_off()348 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_on_finish()364 int cpu = MPIDR_AFFLVL0_VAL(mpidr); in plat_mtk_power_domain_suspend()
33 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
29 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr); in plat_core_pos_by_mpidr()
57 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); in marvell_check_mpidr()
63 (MPIDR_AFFLVL0_VAL(mpidr) >= FPGA_MAX_PE_PER_CPU)) { in plat_core_pos_by_mpidr()
269 boot_cpu = MPIDR_AFFLVL0_VAL(read_mpidr_el1()); in nonboot_cpus_off()301 cpu = MPIDR_AFFLVL0_VAL(mpidr); in rockchip_soc_cores_pwr_dm_on()
160 int cpu = MPIDR_AFFLVL0_VAL(read_mpidr()); in go_to_sleep_before_wfi()
128 (1 << (standbywfi + MPIDR_AFFLVL0_VAL(mpidr))) | in brcm_power_down_common()
313 uint32_t coreid = MPIDR_AFFLVL0_VAL(mpidr); in ihost_power_on_secondary_core()
255 boot_cpu = MPIDR_AFFLVL0_VAL(read_mpidr()); in nonboot_cpus_off()
43 #define MPIDR_AFFLVL0_VAL(mpidr) \ macro
47 #define MPIDR_AFFLVL0_VAL(mpidr) \ macro
1147 aff0 = MPIDR_AFFLVL0_VAL(target); in gicv3_raise_secure_g0_sgi()