| /external/arm-trusted-firmware/plat/arm/common/ |
| D | arm_topology.c | 25 valid_mask = ~(MPIDR_AFFLVL_MASK | in arm_check_mpidr()
26 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | in arm_check_mpidr()
27 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | in arm_check_mpidr()
28 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT)); in arm_check_mpidr()
29 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
30 cpu_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
31 pe_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in arm_check_mpidr()
35 MPIDR_AFFLVL_MASK); in arm_check_mpidr()
37 MPIDR_AFFLVL_MASK); in arm_check_mpidr()
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/ |
| D | plat_topology.c | 47 if (mpidr & (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) { in plat_core_pos_by_mpidr()
59 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
60 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/drivers/arm/css/scpi/ |
| D | css_scpi.c | 199 cpu = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
200 cluster = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
202 cpu = mpidr & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
203 cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_css_power_state()
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| /external/arm-trusted-firmware/plat/layerscape/common/ |
| D | ls_topology.c | 20 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in ls_check_mpidr()
21 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in ls_check_mpidr()
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| /external/arm-trusted-firmware/plat/intel/soc/common/ |
| D | socfpga_topology.c | 36 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
37 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/arm/board/a5ds/ |
| D | a5ds_topology.c | 38 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
39 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /external/arm-trusted-firmware/plat/amlogic/common/ |
| D | aml_topology.c | 43 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
44 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/rpi/common/ |
| D | rpi3_topology.c | 46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/qemu/common/ |
| D | topology.c | 47 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
48 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey/ |
| D | hikey_topology.c | 52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /external/arm-trusted-firmware/plat/hisilicon/hikey960/ |
| D | hikey960_topology.c | 52 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
53 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/mediatek/mt8173/ |
| D | plat_topology.c | 46 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
47 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/mediatek/mt8183/ |
| D | plat_topology.c | 45 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
46 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
|
| /external/arm-trusted-firmware/plat/socionext/uniphier/ |
| D | uniphier_topology.c | 31 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
35 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/socionext/synquacer/ |
| D | sq_topology.c | 19 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
23 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/renesas/common/ |
| D | plat_topology.c | 33 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
34 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/qemu/qemu_sbsa/ |
| D | sbsa_topology.c | 49 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
50 cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/include/arch/aarch64/ |
| D | arch.h | 31 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
32 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
34 #define MPIDR_AFFLVL_MASK ULL(0xff) macro
48 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
50 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
52 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
54 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
[all …]
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| /external/arm-trusted-firmware/include/arch/aarch32/ |
| D | arch.h | 28 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
29 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
31 #define MPIDR_AFFLVL_MASK U(0xff) macro
44 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
46 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
48 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
52 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
55 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)|\
56 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT)|\
57 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
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| /external/arm-trusted-firmware/drivers/arm/css/scp/ |
| D | css_pm_scpi.c | 103 element = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in css_scp_get_power_state()
105 element = mpidr & MPIDR_AFFLVL_MASK; in css_scp_get_power_state()
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| /external/arm-trusted-firmware/plat/qti/common/src/ |
| D | qti_common.c | 63 cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in plat_qti_my_cluster_pos()
65 cluster_id = (mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK; in plat_qti_my_cluster_pos()
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| /external/arm-trusted-firmware/plat/brcm/common/ |
| D | brcm_scpi.c | 189 cpu = mpidr & MPIDR_AFFLVL_MASK; in scpi_get_brcm_power_state()
190 cluster = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK; in scpi_get_brcm_power_state()
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| /external/arm-trusted-firmware/plat/rockchip/common/ |
| D | plat_topology.c | 26 cpu_id = mpidr & MPIDR_AFFLVL_MASK; in plat_core_pos_by_mpidr()
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| /external/arm-trusted-firmware/plat/marvell/armada/common/ |
| D | marvell_topology.c | 51 MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) in marvell_check_mpidr()
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| /external/arm-trusted-firmware/plat/mediatek/mt8192/aarch64/ |
| D | plat_helpers.S | 46 mov x1, #MPIDR_AFFLVL_MASK
|