| /external/llvm-project/llvm/test/CodeGen/Mips/GlobalISel/instruction-select/ |
| D | float_constants.mir | 21 ; FP32: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
27 ; FP64: [[MTC1_:%[0-9]+]]:fgr32 = MTC1 [[ORi]]
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 118 Opc = Mips::MTC1; in copyPhysReg()
369 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
372 expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false); in expandPostRAPseudo()
378 expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); in expandPostRAPseudo()
652 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsAsmPrinter.cpp | 777 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
816 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 368 def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
605 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>;
606 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>;
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| D | MipsFastISel.cpp | 350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 122 Opc = Mips::MTC1; in copyPhysReg()
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
815 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsInstructionSelector.cpp | 504 MachineInstrBuilder MTC1 = in select() local
505 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
506 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
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| D | MipsAsmPrinter.cpp | 883 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 531 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
904 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
905 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
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| D | MipsRegisterBankInfo.cpp | 150 case Mips::MTC1: in isFloatingPointOpcodeDef()
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| D | MipsCallLowering.cpp | 157 MIRBuilder.buildInstr(Mips::MTC1) in assignValueToReg()
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| D | MipsScheduleP5600.td | 563 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| D | MipsFastISel.cpp | 397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 122 Opc = Mips::MTC1; in copyPhysReg()
448 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); in expandPostRAPseudo()
452 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); in expandPostRAPseudo()
459 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); in expandPostRAPseudo()
829 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); in expandBuildPairF64()
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| D | MipsInstructionSelector.cpp | 603 MachineInstrBuilder MTC1 = in select() local
604 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg}); in select()
605 if (!MTC1.constrainAllUses(TII, TRI, RBI)) in select()
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| D | MipsAsmPrinter.cpp | 883 if (Opcode == Mips::MTC1) { in EmitInstrRegReg()
923 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1; in EmitSwapFPIntParams()
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| D | MipsInstrFPU.td | 564 def MTC1 : MMRel, StdMMR6Rel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1,
937 def : MipsPat<(f32 fpimm0), (MTC1 ZERO)>, ISA_MIPS1;
938 def : MipsPat<(f32 fpimm0neg), (FNEG_S (MTC1 ZERO))>, ISA_MIPS1;
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| D | MipsScheduleP5600.td | 564 def : InstRW<[P5600WriteMoveGPRToFPU], (instrs CTC1, MTC1, MTC1_D64, MTHC1_D32,
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| D | MipsFastISel.cpp | 397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
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| D | MipsScheduleGeneric.td | 872 MFHC1_D64, MTC1, MTC1_D64,
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeMIPS_common.c | 219 #define MTC1 (HI(17) | (4 << 21)) macro
1567 FAIL_IF(push_inst(compiler, MTC1 | flags | T(src) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
1578 FAIL_IF(push_inst(compiler, MTC1 | flags | T(TMP_REG1) | FS(TMP_FREG1), MOVABLE_INS)); in sljit_emit_fop1_conv_f64_from_sw()
|
| /external/llvm-project/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | select-dbl.ll | 102 ; MM32R3: mtc1 $7, $f2 # <MCInst #{{.*}} MTC1
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| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 1211 1867870U, // MTC1
3000 0U, // MTC1
4717 // ADDIUS5_MM, CTC1, CTC1_MM, DAHI, DATI, DMTC1, MTC1, MTC1_MM, MTHI_DSP,...
4804 // CTC1, CTC1_MM, DMTC1, MTC1, MTC1_MM, MTHC1_D32, MTHC1_D64, MTHC1_MM, M...
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3400 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3530 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3533 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3534 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3372 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI); in expandLoadSingleImmToFPR()
3502 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
3505 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI); in expandLoadDoubleImmToFPR()
3506 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI); in expandLoadDoubleImmToFPR()
|