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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dnon-entry-alloca.ll2 …amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,DEFAULTSIZE,MUBUF %s
3 …dgpu-assume-dynamic-stack-object-size=1024 < %s | FileCheck -check-prefixes=GCN,ASSUME1024,MUBUF %s
16 ; MUBUF-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
17 ; MUBUF: ; %bb.0: ; %entry
18 ; MUBUF-NEXT: s_add_u32 flat_scratch_lo, s6, s9
19 ; MUBUF-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
20 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
21 ; MUBUF-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x8
22 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
23 ; MUBUF-NEXT: s_movk_i32 s32, 0x400
[all …]
Dlocal-stack-alloc-block-sp-reference.ll2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx906 < %s | FileCheck -check-prefixes=GCN,GFX9,MUBUF
20 ; MUBUF-LABEL: local_stack_offset_uses_sp:
21 ; MUBUF: ; %bb.0: ; %entry
22 ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
23 ; MUBUF-NEXT: s_add_u32 flat_scratch_lo, s6, s9
24 ; MUBUF-NEXT: s_addc_u32 flat_scratch_hi, s7, 0
25 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
26 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
27 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
28 ; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1
[all …]
Dstack-pointer-offset-relative-frameindex.ll2 ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=MUBUF %s
5 ; FIXME: The MUBUF loads in this test output are incorrect, their SOffset
7 ; rely on the frame index argument of MUBUF stack accesses to survive until PEI
11 ; into the MUBUF instruction, and so we end up emitting an incorrect offset.
17 ; MUBUF-LABEL: kernel_background_evaluate:
18 ; MUBUF: ; %bb.0: ; %entry
19 ; MUBUF-NEXT: s_load_dword s0, s[0:1], 0x24
20 ; MUBUF-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
21 ; MUBUF-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
22 ; MUBUF-NEXT: s_mov_b32 s38, -1
[all …]
Dmemcpy-fixed-align.ll2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s -check-prefix=MUBUF
7 ; MUBUF-LABEL: memcpy_fixed_align:
8 ; MUBUF: ; %bb.0:
9 ; MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10 ; MUBUF-NEXT: global_load_dword v0, v[1:2], off offset:36
11 ; MUBUF-NEXT: global_load_dword v11, v[1:2], off offset:32
12 ; MUBUF-NEXT: global_load_dwordx4 v[3:6], v[1:2], off offset:16
13 ; MUBUF-NEXT: global_load_dwordx4 v[7:10], v[1:2], off
14 ; MUBUF-NEXT: s_waitcnt vmcnt(3)
15 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:36
[all …]
Dmulti-dword-vgpr-spill.ll1 …ble-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck %s -check-prefixes=GCN,MUBUF
5 ; MUBUF-DAG: buffer_store_dword v{{.*}} offset:16 ; 4-byte Folded Spill
6 ; MUBUF-DAG: buffer_store_dword v{{.*}} offset:20 ; 4-byte Folded Spill
11 ; MUBUF-DAG: buffer_load_dword v{{.*}} offset:16 ; 4-byte Folded Reload
12 ; MUBUF-DAG: buffer_load_dword v{{.*}} offset:20 ; 4-byte Folded Reload
33 ; MUBUF-DAG: buffer_store_dword v{{.*}} offset:16 ; 4-byte Folded Spill
34 ; MUBUF-DAG: buffer_store_dword v{{.*}} offset:20 ; 4-byte Folded Spill
39 ; MUBUF-DAG: buffer_load_dword v{{.*}} offset:16 ; 4-byte Folded Reload
40 ; MUBUF-DAG: buffer_load_dword v{{.*}} offset:20 ; 4-byte Folded Reload
61 ; MUBUF-DAG: buffer_store_dword v{{.*}} offset:32 ; 4-byte Folded Spill
[all …]
Dcallee-frame-setup.ll1 …pu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,MUBUF %s
2 …=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,MUBUF %s
16 ; MUBUF-NEXT: s_mov_b32 [[FP_COPY:s4]], s33
37 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32{{$}}
52 ; MUBUF-NEXT: s_mov_b32 [[FP_COPY:s4]], s33
55 ; MUBUF-NEXT: s_add_u32 s32, s32, 0x200
58 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4{{$}}
60 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x200
75 ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s32{{$}}
89 ; MUBUF-NEXT: buffer_store_dword [[CSR_VGPR:v[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded …
[all …]
Dframe-index-elimination.ll1 …gpu-sroa=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,MUBUF %s
2 …erify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9,GFX9-MUBUF,MUBUF %s
13 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
18 ; MUBUF-NOT: v_mov
38 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 v0, 6, s32
42 ; GFX9-MUBUF-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
43 ; GFX9-MUBUF-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
63 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s32
64 ; GFX9-MUBUF-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
85 ; GFX9-MUBUF: v_lshrrev_b32_e64 v0, 6, s32
[all …]
Dpei-scavenge-sgpr-gfx9.mir2 …cpu=gfx900 -verify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck --check-prefix=MUBUF %s
25 ; MUBUF-LABEL: name: scavenge_sgpr_pei_no_sgprs
26 ; MUBUF: liveins: $sgpr27, $vgpr1
27 ; MUBUF: $sgpr27 = frame-setup COPY $sgpr33
28 ; MUBUF: $sgpr4 = frame-setup S_ADD_U32 $sgpr32, 524224, implicit-def $scc
29 ; MUBUF: $sgpr33 = frame-setup S_AND_B32 killed $sgpr4, 4294443008, implicit-def $scc
30 ; MUBUF: $sgpr32 = frame-setup S_ADD_U32 $sgpr32, 1572864, implicit-def $scc
31 …; MUBUF: S_NOP 0, implicit-def $sgpr4, implicit-def $sgpr5, implicit-def $sgpr6, implicit-def $sgp…
32 ; MUBUF: $vgpr0 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
33 ; MUBUF: $vgpr2 = V_LSHRREV_B32_e64 6, $sgpr33, implicit $exec
[all …]
Dcall-preserved-registers.ll1 …mdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MUBUF %s
2 …hsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MUBUF %s
3 …hsa -mcpu=gfx900 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MUBUF %s
26 ; MUBUF: buffer_store_dword
38 ; MUBUF-DAG: v_readlane_b32 s4, v40, 2
39 ; MUBUF-DAG: v_readlane_b32 s5, v40, 3
46 ; MUBUF: buffer_load_dword
57 ; MUBUF: buffer_store_dword v40
62 ; MUBUF: s_add_u32 s32, s32, 0x400
68 ; MUBUF: buffer_load_dword v40
[all …]
Dload-lo16.ll2 …r=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900,GFX900-MUBUF %s
1181 ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg:
1182 ; GFX900-MUBUF: ; %bb.0: ; %entry
1183 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
1184 ; GFX900-MUBUF-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094
1185 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
1186 ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
1187 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
1188 ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
1230 ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg:
[all …]
Dsgpr-spill.mir1 …erify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GCN64,MUBUF %s
2 …erify-machineinstrs -run-pass=prologepilog %s -o - | FileCheck -check-prefixes=CHECK,GCN32,MUBUF %s
16 # MUBUF: BUFFER_STORE_DWORD_OFFSET killed $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
24 # MUBUF: BUFFER_STORE_DWORD_OFFSET $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 4
35 # MUBUF: BUFFER_STORE_DWORD_OFFSET killed $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 8
47 # MUBUF: BUFFER_STORE_DWORD_OFFSET $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 8
62 # MUBUF: BUFFER_STORE_DWORD_OFFSET killed $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 16
76 # MUBUF: BUFFER_STORE_DWORD_OFFSET killed $vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 28
91 # MUBUF: BUFFER_STORE_DWORD_OFFSET {{(killed )?}}$vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 44
109 # MUBUF: BUFFER_STORE_DWORD_OFFSET {{(killed )?}}$vgpr{{[0-9]+}}, ${{(sgpr[0-9_]+)*}}, $sgpr33, 64
[all …]
Dspill-offset-calculation.ll1 …ble-misched=0 -post-RA-scheduler=0 -stress-regalloc=8 < %s | FileCheck -check-prefixes=GCN,MUBUF %s
17 …; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4092 ; 4-byte Folde…
40 ; MUBUF: s_mov_b32 s6, 0x40000
41 ; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s6 ; 4-byte Folded Spill
81 ; MUBUF: s_add_u32 s32, s32, 0x40000
82 ; MUBUF: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s32 ; 4-byte Folded Spill
83 ; MUBUF: s_sub_u32 s32, s32, 0x40000
100 ; MUBUF: s_add_u32 s32, s32, 0x40000
101 ; MUBUF: buffer_load_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s32 ; 4-byte Folded Reload
102 ; MUBUF: s_sub_u32 s32, s32, 0x40000
[all …]
Dscratch-simple.ll1 …gent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,SI,SIVI,MUBUF %s
2 …gent-register-indexing -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,VI,SIVI,MUBUF %s
3 …-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX9,GFX9_10,MUBUF,GFX9-MUBUF,GFX9_10-MUBUF %s
5 …strs < %s | FileCheck --check-prefixes=GCN,GFX10_W32,GFX9_10,MUBUF,GFX10_W32-MUBUF,GFX9_10-MUBUF %s
6 …strs < %s | FileCheck --check-prefixes=GCN,GFX10_W64,GFX9_10,MUBUF,GFX10_W64-MUBUF,GFX9_10-MUBUF %s
52 ; MUBUF-DAG: s_mov_b32 s0, SCRATCH_RSRC_DWORD0
53 ; MUBUF-DAG: s_mov_b32 s1, SCRATCH_RSRC_DWORD1
54 ; MUBUF-DAG: s_mov_b32 s2, -1
57 ; GFX9-MUBUF-DAG: s_mov_b32 s3, 0xe00000
58 ; GFX10_W32-MUBUF-DAG: s_mov_b32 s3, 0x31c16000
[all …]
Dmubuf.ll4 ;;; MUBUF LOAD TESTS
7 ; MUBUF load with an immediate byte offset that fits into 12-bits
18 ; MUBUF load with the largest possible immediate offset
29 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
41 ; MUBUF load with a 12-bit immediate offset and a register offset
88 ;;; MUBUF STORE TESTS
91 ; MUBUF store with an immediate byte offset that fits into 12-bits
101 ; MUBUF store with the largest possible immediate offset
112 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
123 ; MUBUF store with a 12-bit immediate offset and a register offset
Dstore-hi16.ll1 …strs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefixes=GCN,GFX900,GFX9,GFX900-MUBUF %s
393 ; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen{{$}}
413 ; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen{{$}}
433 ; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], 0 offen{{$}}
452 ; GFX900-MUBUF-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], 0 offen{{$}}
472 ; GFX900-MUBUF-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], 0 offen{{$}}
490 ; GFX900-MUBUF: buffer_store_short_d16_hi v0, off, s[0:3], s32 offset:4094{{$}}
512 ; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], 0{{$}}
534 ; GFX900-MUBUF-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], 0{{$}}
648 ; GFX900-MUBUF: buffer_store_dword
[all …]
Dload-hi16.ll1 …r=-promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX900,GFX900-MUBUF %s
497 ; GFX900-MUBUF: buffer_load_short_d16_hi v0, off, s[0:3], s32 offset:4094{{$}}
517 ; GFX900-MUBUF: buffer_load_short_d16_hi v0, off, s[0:3], s32 offset:4094{{$}}
557 ; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:4094{{$}}
577 ; GFX900-MUBUF: buffer_load_ubyte_d16_hi v0, off, s[0:3], s32 offset:4095{{$}}
598 ; GFX900-MUBUF: buffer_load_ubyte_d16_hi v0, off, s[0:3], s32 offset:4095{{$}}
620 ; GFX900-MUBUF: buffer_load_sbyte_d16_hi v0, off, s[0:3], s32 offset:4095{{$}}
642 ; GFX900-MUBUF: buffer_load_sbyte_d16_hi v0, off, s[0:3], s32 offset:4095{{$}}
663 ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], 0 offset:4094{{$}}
684 ; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], 0 offset:4094{{$}}
[all …]
Dschedule-global-loads.ll23 ; an MUBUF load which does not have a vaddr operand.
Dlocal-stack-slot-offset.ll6 ; MUBUF instructions, so a new base register is needed. This used to not
/external/llvm/test/CodeGen/AMDGPU/
Dmubuf.ll6 ;;; MUBUF LOAD TESTS
9 ; MUBUF load with an immediate byte offset that fits into 12-bits
20 ; MUBUF load with the largest possible immediate offset
31 ; MUBUF load with an immediate byte offset that doesn't fit into 12-bits
43 ; MUBUF load with a 12-bit immediate offset and a register offset
88 ;;; MUBUF STORE TESTS
91 ; MUBUF store with an immediate byte offset that fits into 12-bits
101 ; MUBUF store with the largest possible immediate offset
112 ; MUBUF store with an immediate byte offset that doesn't fit into 12-bits
123 ; MUBUF store with a 12-bit immediate offset and a register offset
Dschedule-global-loads.ll24 ; an MUBUF load which does not have a vaddr operand.
/external/mesa3d/src/amd/compiler/
Daco_opcodes.py43 MUBUF = 10 variable in Format
88 elif self == Format.MUBUF:
1249 MUBUF = { variable
1331 for (gfx6, gfx7, gfx8, gfx9, gfx10, name) in MUBUF:
1332 opcode(name, gfx7, gfx9, gfx10, Format.MUBUF, is_atomic = "atomic" in name)
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIPostRABundler.cpp93 const uint64_t MemFlags = SIInstrFlags::MTBUF | SIInstrFlags::MUBUF | in runOnMachineFunction()
/external/llvm/docs/
DAMDGPUUsage.rst55 MUBUF Instructions
57 All non-atomic MUBUF instructions are supported.
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td928 // MUBUF Instructions
2159 (!cast<MUBUF>(opcode # _OFFSET) $rsrc, $soffset, (as_i16imm $offset),
2167 (!cast<MUBUF>(opcode # _IDXEN) $vindex, $rsrc, $soffset, (as_i16imm $offset),
2175 (!cast<MUBUF>(opcode # _OFFEN) $voffset, $rsrc, $soffset, (as_i16imm $offset),
2183 (!cast<MUBUF>(opcode # _BOTHEN)
2203 (!cast<MUBUF>(opcode # _OFFSET) $vdata, $rsrc, $soffset, (as_i16imm $offset),
2211 (!cast<MUBUF>(opcode # _IDXEN) $vdata, $vindex, $rsrc, $soffset,
2220 (!cast<MUBUF>(opcode # _OFFEN) $vdata, $voffset, $rsrc, $soffset,
2229 (!cast<MUBUF>(opcode # _BOTHEN)
2252 (!cast<MUBUF>(opcode # _RTN_OFFSET) $vdata_in, $rsrc, $soffset,
[all …]
DSIInstrFormats.td38 field bits<1> MUBUF = 0;
74 let TSFlags{16} = MUBUF;
686 class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> :
691 let MUBUF = 1;

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