Searched refs:MUHU (Results 1 – 17 of 17) sorted by relevance
/external/pcre/dist2/src/sljit/ |
D | sljitNativeMIPS_common.c | 222 #define MUHU (HI(0) | (3 << 6) | LO(25)) macro 1244 …FAIL_IF(push_inst(compiler, (op == SLJIT_LMUL_UW ? MUHU : MUH) | S(SLJIT_R0) | T(SLJIT_R1) | D(TMP… in sljit_emit_op0()
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/external/llvm/lib/Target/Mips/ |
D | Mips32r6InstrInfo.td | 825 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
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/external/llvm-project/llvm/lib/Target/Mips/ |
D | Mips32r6InstrInfo.td | 945 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
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D | MipsScheduleGeneric.td | 197 def : InstRW<[GenericWriteMul], (instrs MUH, MUHU, MULU, MUL_R6)>;
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
D | Mips32r6InstrInfo.td | 945 def MUHU : R6MMR6Rel, MUHU_ENC, MUHU_DESC, ISA_MIPS32R6;
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D | MipsScheduleGeneric.td | 197 def : InstRW<[GenericWriteMul], (instrs MUH, MUHU, MULU, MUL_R6)>;
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/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
D | MipsGenSubtargetInfo.inc | 1122 {DBGFIELD("MUHU") 1, false, false, 12, 2, 4, 1, 0, 0}, // #862 2806 {DBGFIELD("MUHU") 16383, false, false, 0, 0, 0, 0, 0, 0}, // #862
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D | MipsGenMCCodeEmitter.inc | 2106 UINT64_C(217), // MUHU 5041 case Mips::MUHU: 11568 CEFBS_HasStdEnc_HasMips32r6_NotInMicroMips, // MUHU = 2093
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D | MipsGenAsmWriter.inc | 3334 268459657U, // MUHU 6088 0U, // MUHU
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D | MipsGenInstrInfo.inc | 2108 MUHU = 2093, 3642 MUHU = 862, 6954 …093, 3, 1, 4, 862, 0, 0x6ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr }, // Inst #2093 = MUHU 16645 { Mips::MUHU, Mips::MUHU, Mips::MUHU_MMR6 },
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D | MipsGenFastISel.inc | 1821 return fastEmitInst_rr(Mips::MUHU, &Mips::GPR32RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
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D | MipsGenDisassemblerTables.inc | 6291 /* 272 */ MCD::OPC_Decode, 173, 16, 50, // Opcode: MUHU
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D | MipsGenAsmMatcher.inc | 7213 …{ 6833 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, AMFBS_HasS…
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D | MipsGenGlobalISel.inc | 21433 …// (mulhu:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt) => (MUHU:{ *:[i32] }… 21434 GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/Mips::MUHU,
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D | MipsGenDAGISel.inc | 26051 /* 49320*/ OPC_MorphNodeTo1, TARGET_VAL(Mips::MUHU), 0, 26054 // Dst: (MUHU:{ *:[i32] } GPR32Opnd:{ *:[i32] }:$rs, GPR32Opnd:{ *:[i32] }:$rt)
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/external/capstone/arch/Mips/ |
D | MipsGenAsmWriter.inc | 1233 134241300U, // MUHU 3022 0U, // MUHU
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D | MipsGenDisassemblerTables.inc | 3880 /* 234 */ MCD_OPC_Decode, 192, 9, 35, // Opcode: MUHU
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