Searched refs:MVEBU_REGS_BASE (Results 1 – 18 of 18) sorted by relevance
25 #define MVEBU_REGS_BASE 0xD0000000 macro32 #define DEVICE0_BASE MVEBU_REGS_BASE57 #define MVEBU_NB_REGS_BASE (MVEBU_REGS_BASE + 0x13000)58 #define MVEBU_SB_REGS_BASE (MVEBU_REGS_BASE + 0x18000)69 #define MVEBU_NB_SB_IRQ_REG_BASE (MVEBU_REGS_BASE + 0x8A00)83 #define MVEBU_DRAM_REG_BASE (MVEBU_REGS_BASE)89 #define MVEBU_SB_WAKEUP_REG_BASE (MVEBU_REGS_BASE + 0x19000)95 #define MVEBU_PMSU_REG_BASE (MVEBU_REGS_BASE + 0x14000)101 #define MVEBU_NB_STEP_DOWN_REG_BASE (MVEBU_REGS_BASE + 0x12800)107 #define MVEBU_CS_MMAP_REG_BASE (MVEBU_REGS_BASE + 0x200)[all …]
121 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)122 #define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE)123 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)166 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
17 #define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC)28 #define MVEBU_REGS_BASE 0xF0000000 macro30 #define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE35 #define MVEBU_RFU_BASE (MVEBU_REGS_BASE + 0x6F0000)41 #define MVEBU_MISC_SOC_BASE (MVEBU_REGS_BASE + 0x6F4300)43 #define MVEBU_CCU_BASE(ap_index) (MVEBU_REGS_BASE + 0x4000)46 #define MVEBU_LLC_BASE(ap_index) (MVEBU_REGS_BASE + 0x8000)47 #define MVEBU_DRAM_MAC_BASE (MVEBU_REGS_BASE + 0x20000)48 #define MVEBU_DRAM_PHY_BASE (MVEBU_REGS_BASE + 0x20000)49 #define MVEBU_SMMU_BASE (MVEBU_REGS_BASE + 0x100000)[all …]
131 #define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE)132 #define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE)171 #define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x512000)
27 #define MVEBU_CCU_RVBAR(cpu) (MVEBU_REGS_BASE + 0x640 + (cpu * 4))28 #define MVEBU_CCU_CPU_UN_RESET(cpu) (MVEBU_REGS_BASE + 0x650 + (cpu * 4))75 (MVEBU_REGS_BASE + 0x6F8230)89 (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10))99 (MVEBU_REGS_BASE + 0x1A50 + \107 (MVEBU_REGS_BASE + 0x680000 + 0x100)324 mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4); in plat_marvell_cpu_on()
71 mv_pm_ipc_init(mss_pm_crtl->ipc_base_address | MVEBU_REGS_BASE); in marvell_bl31_mss_init()
25 #define MSS_SISR (MVEBU_REGS_BASE + 0x5800D0)26 #define MSS_SISTR (MVEBU_REGS_BASE + 0x5800D8)
129 return MVEBU_REGS_BASE + 0x580000; in bl2_plat_get_ap_mss_regs()
16 #define MVEBU_SF_REG (MVEBU_REGS_BASE + 0x40)18 #define MVEBU_DFX_REG(cluster_id) (MVEBU_REGS_BASE + 0x6F82A0 + \
14 #define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \16 #define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \18 #define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + (base) + \
67 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); in mrvl_sip_smc_handler()
269 if (mvebu_get_dram_size(MVEBU_REGS_BASE) <= _2GB_) in cpu_wins_init()
38 #define MVEBU_CPU_1_RESET_VECTOR (MVEBU_REGS_BASE + 0x14044)39 #define MVEBU_CPU_1_RESET_REG (MVEBU_REGS_BASE + 0xD00C)
58 #define MVEBU_MSS_GTCR_REG (MVEBU_REGS_BASE + 0x581000)66 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
70 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580)
12 #define MSS_SRAM_PM_CONTROL_BASE (MVEBU_REGS_BASE + 0x520000)
119 ret = mvebu_get_dram_size(MVEBU_REGS_BASE); in mrvl_sip_smc_handler()
26 #define COMPHY_INDIRECT_REG (MVEBU_REGS_BASE + 0xE0178)29 #define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)30 #define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)