Searched refs:MVNS (Results 1 – 12 of 12) sorted by relevance
| /external/vixl/test/aarch32/config/ |
| D | cond-rd-operand-const-a32.json | 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, #<const> ; A1
78 "Mvns" // MVNS{<c>}{<q>} <Rd>, #<const> ; A1
|
| D | cond-rd-operand-rn-t32.json | 49 "Mvns", // MVNS{<q>} <Rd>, <Rm> ; T1
50 // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-operand-const-t32.json | 37 "Mvns", // MVNS{<c>}{<q>} <Rd>, #<const> ; T1
|
| D | cond-rd-operand-rn-shift-amount-1to31-a32.json | 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-operand-rn-shift-amount-1to32-a32.json | 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
|
| D | cond-rd-operand-rn-shift-rs-a32.json | 34 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs> ; A1
|
| D | cond-rd-operand-rn-shift-amount-1to32-t32.json | 40 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-operand-rn-shift-amount-1to31-t32.json | 39 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; T2
|
| D | cond-rd-operand-rn-a32.json | 42 "Mvns", // MVNS{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount> } ; A1
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 309 "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
322 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
326 (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>;
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleR52.td | 309 "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
322 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
326 (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>;
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_T2_32.c | 146 #define MVNS 0x43c0 macro
797 return push_inst16(compiler, MVNS | RD3(dst) | RN3(arg2)); in emit_op_imm()
|