Searched refs:MinVecRegSize (Results 1 – 3 of 3) sorted by relevance
322 MinVecRegSize = MinVectorRegSizeOption; in BoUpSLP()383 return MinVecRegSize; in getMinVecRegSize()899 unsigned MinVecRegSize; // Set by cl::opt (default: 128). member in llvm::slpvectorizer::BoUpSLP1474 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || VTSize != DL.getTypeStoreSizeInBits(T)) in canMapToVector()3962 unsigned MinVecRegSize; member in HorizontalReduction3964 HorizontalReduction(unsigned MinVecRegSize) in HorizontalReduction() argument3967 MinVecRegSize(MinVecRegSize) {} in HorizontalReduction()4000 ReduxWidth = MinVecRegSize / DL.getTypeSizeInBits(Ty); in matchAssociativeReduction()
557 MinVecRegSize = MinVectorRegSizeOption; in BoUpSLP()559 MinVecRegSize = TTI->getMinVectorRegisterBitWidth(); in BoUpSLP()645 return MinVecRegSize; in getMinVecRegSize()2217 unsigned MinVecRegSize; // Set by cl::opt (default: 128). member in llvm::slpvectorizer::BoUpSLP3137 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || VTSize != DL.getTypeStoreSizeInBits(T)) in canMapToVector()
570 MinVecRegSize = MinVectorRegSizeOption; in BoUpSLP()572 MinVecRegSize = TTI->getMinVectorRegisterBitWidth(); in BoUpSLP()741 return MinVecRegSize; in getMinVecRegSize()2372 unsigned MinVecRegSize; // Set by cl::opt (default: 128). member in llvm::slpvectorizer::BoUpSLP3308 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || VTSize != DL.getTypeStoreSizeInBits(T)) in canMapToVector()